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authorJoshua Yun <joshua@joshuayun.com>2025-05-17 11:04:47 -0500
committerJoshua Yun <joshua@joshuayun.com>2025-05-17 11:04:47 -0500
commite580017e209a0888c3f5a2063d265de50c66c56b (patch)
tree28ba8b4784fa33d539571e26f00b0017ca5ab173 /core/rtl/fetch.sv
parent86021b3616c24efe38d8869b45d201bf24fe9a07 (diff)
downloadriscv-processor-e580017e209a0888c3f5a2063d265de50c66c56b.tar.gz
initial commit
Diffstat (limited to 'core/rtl/fetch.sv')
-rw-r--r--core/rtl/fetch.sv22
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diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv
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--- a/core/rtl/fetch.sv
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-module fetch
-import riscv_types::*;
-(
- input logic clk,
- input logic rst_l,
-
- // IMEM interface
- output logic [31:0] if_imem_addr_IF
-);
-
-logic [31:0] pc_IF;
-logic [31:0] pcNxt_IF;
-
-assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, addresses are always 32 bit aligned
- // TODO: Find out if 32 is the best fetching width vs 16
-
-// Program Counter (PC)
-assign pcNxt_IF = pc_IF + 32'd4;
-
-AFFR #(.WIDTH(32)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) );
-
-endmodule