feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64

3 files changed, 50 insertions, 11 deletions

diff --git a/core/rtl/core.sv b/core/rtl/core.sv
index 5f64e7a..d9a51dd 100644
--- a/core/rtl/core.sv
+++ b/core/rtl/core.sv
@@ -1,10 +1,11 @@
 module core
+import riscv_types::*;
 (
   input  logic clk,
   input  logic rst_l,
   // Instruction mem interface
-  output logic [63:0] if_imem_addr_IF,
-  input  logic [63:0] imem_id_instr_ID
+  output logic [31:0] if_imem_addr_IF,
+  input  logic [31:0] imem_id_instr_ID
 
   // Data mem interface 
 );
@@ -15,8 +16,10 @@ fetch fetch0 (
   .if_imem_addr_IF(if_imem_addr_IF)
 );
 
-always @ (posedge clk) begin
-  $display("Instruction: %x", imem_id_instr_ID);
-end
+decode decode0 (
+  .clk(clk),
+  .rst_l(rst_l),
+  .imem_id_instr_ID(imem_id_instr_ID)
+);
 
 endmodule
diff --git a/core/rtl/decode.sv b/core/rtl/decode.sv
new file mode 100644
index 0000000..e337e11
--- /dev/null
+++ b/core/rtl/decode.sv
@@ -0,0 +1,34 @@
+module decode
+import riscv_types::*;
+#(
+  )
+  (
+    input  logic        clk,
+    input  logic        rst_l,
+
+    // I-MEM Interface
+    input  logic [31:0] imem_id_instr_ID
+  );
+
+opcode_t instrOpCode_ID;
+
+assign instrOpCode_ID = opcode_t'(imem_id_instr_ID[6:0]);
+
+always_ff @(posedge clk) begin
+  $display("Instruction: %x", imem_id_instr_ID);
+  case (instrOpCode_ID)
+    INSTR_TYPE_LUI:    begin $display("Instr type: LUI"); end
+    INSTR_TYPE_AUIPC:  begin $display("Instr type: AUIPC"); end
+    INSTR_TYPE_JAL:    begin $display("Instr type: JAL"); end
+    INSTR_TYPE_JALR:   begin $display("Instr type: JALR"); end
+    INSTR_TYPE_BR:     begin $display("Instr type: BR"); end
+    INSTR_TYPE_LD:     begin $display("Instr type: LD"); end
+    INSTR_TYPE_ST:     begin $display("Instr type: ST"); end
+    INSTR_TYPE_IMM:    begin $display("Instr type: IMM"); end
+    INSTR_TYPE_REG:    begin $display("Instr type: REG"); end
+    INSTR_TYPE_CSR:    begin $display("Instr type: CSR"); end
+    default:           begin $display("Instr type: Unknown"); end
+  endcase
+end
+
+endmodule
diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv
index 7cbff6a..d2b5ed0 100644
--- a/core/rtl/fetch.sv
+++ b/core/rtl/fetch.sv
@@ -1,20 +1,22 @@
 module fetch
+import riscv_types::*;
 (
   input  logic clk,
   input  logic rst_l,
 
   // IMEM interface
-  output logic [63:0] if_imem_addr_IF
+  output logic [31:0] if_imem_addr_IF
 );
 
-logic [63:0] pc_IF;
-logic [63:0] pcNxt_IF;
+logic [31:0] pc_IF;
+logic [31:0] pcNxt_IF;
 
-assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, truncate addresses to be 64 bit aligned?
+assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, addresses are always 32 bit aligned
+                                // TODO: Find out if 32 is the best fetching width vs 16
 
 // Program Counter (PC)
-assign pcNxt_IF = pc_IF + 64'd4;
+assign pcNxt_IF = pc_IF + 32'd4;
 
-AFFR #(.WIDTH(64)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) );
+AFFR #(.WIDTH(32)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) );
 
 endmodule