feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64

3 files changed, 35 insertions, 16 deletions

diff --git a/core/tb/.gitignore b/core/tb/.gitignore
new file mode 100644
index 0000000..b5295dc
--- /dev/null
+++ b/core/tb/.gitignore
@@ -0,0 +1,3 @@
+**.S
+**.bin
+**.o
diff --git a/core/tb/core_tb.sv b/core/tb/core_tb.sv
index 9780df8..3252a13 100644
--- a/core/tb/core_tb.sv
+++ b/core/tb/core_tb.sv
@@ -1,27 +1,38 @@
-module core_tb ();
+module core_tb 
+#(
+  parameter TIMEOUT    = 10,
+  parameter ADDR_WIDTH = 16
+);
 
 logic clk;
 logic rst_l;
 
-logic [63:0] if_imem_addr_IF;
-logic [63:0] imem_id_instr_ID;
+// imem instruction interface
+logic [31:0] if_imem_addr_IF;
+logic [31:0] imem_id_instr_ID;
 
 // Clock Generation
-initial begin
-  repeat(1000) begin
-    clk = ~clk;
-    #1;
-  end
-  $finish();
+always begin
+  clk = #1 ~clk;
 end
 
+// Signal Dump, Test Timeout, and Reset
 initial begin
+  // Dump Setup
+  $dumpfile("dump.fst");
+  $dumpvars;
+
+ // Reset Set up
   rst_l = 1'b0;
   repeat (5) @(posedge clk);
   rst_l = 1'b1;
+
+  // Timeout Setup
+  repeat (TIMEOUT) @(posedge clk);
+  $finish("Test Timed Out"); // TODO Make error & increase timeout length
 end
 
-core_tb_imem #( .ADDR_WIDTH(16) ) imem0 (
+core_tb_imem #( .ADDR_WIDTH(ADDR_WIDTH) ) imem0 (
   .clk(clk),
   .if_imem_addr_IF(if_imem_addr_IF),
   .imem_id_instr_ID(imem_id_instr_ID)
diff --git a/core/tb/core_tb_imem.sv b/core/tb/core_tb_imem.sv
index e66af29..6d3fa92 100644
--- a/core/tb/core_tb_imem.sv
+++ b/core/tb/core_tb_imem.sv
@@ -1,15 +1,15 @@
 module core_tb_imem
 #(
-  parameter ADDR_WIDTH = 64
+  parameter ADDR_WIDTH = 32
 )
 (
   input  logic        clk,
 
   // Fetch Interface
-  input  logic [63:0] if_imem_addr_IF,
+  input  logic [31:0] if_imem_addr_IF,
 
   // Decode Interface
-  output logic [63:0] imem_id_instr_ID
+  output logic [31:0] imem_id_instr_ID
 );
 
 int assembly_file;
@@ -17,10 +17,11 @@ int status_file;
 int error_file;
 string error_message_file;
 
-logic [63:0] imem [(1<<(ADDR_WIDTH))-1:0];
+logic [7:0] imem [0:(1<<(ADDR_WIDTH))-1];
 
+// Fill up memory using the $fopen and $fread syscalls
 initial begin
-  assembly_file = $fopen("/home/joshua/Personal/riscv_linux/core/tb/riscv_arithmetic_basic_test_0.bin", "rb");
+  assembly_file = $fopen("/home/joshua/Personal/riscv-linux/core/tb/riscv_arithmetic_basic_test_0.bin", "rb");
   status_file   = $fread( imem, assembly_file );
   if (status_file == 0) begin
     $ferror( assembly_file, error_message_file );
@@ -29,8 +30,12 @@ initial begin
   $display("Memory Contents Initialized");
 end
 
+// Memory reads, TODO: Should we add a RMASK
 always_ff @ (posedge clk) begin
-  imem_id_instr_ID <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]];
+  imem_id_instr_ID[7:0]   <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]+0]; // 4 bytes read into a single word in RISC-V
+  imem_id_instr_ID[15:8]  <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]+1]; // 4 bytes read into a single word in RISC-V
+  imem_id_instr_ID[23:16] <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]+2]; // 4 bytes read into a single word in RISC-V
+  imem_id_instr_ID[31:24] <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]+3]; // 4 bytes read into a single word in RISC-V
 end
 
 endmodule