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| author | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 17:35:52 -0500 |
|---|---|---|
| committer | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 17:35:52 -0500 |
| commit | 59fd8c25ee1452452cb564d6fe4163b7a9394aef (patch) | |
| tree | 028688a39cd401a40939d86e3bf4a8f5d678d6a4 /fusesoc.conf | |
| parent | c7a29c00b143ff6ee22bb7cffbdd0ae7c21206d1 (diff) | |
| download | riscv-processor-59fd8c25ee1452452cb564d6fe4163b7a9394aef.tar.gz | |
feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete
Diffstat (limited to 'fusesoc.conf')
| -rw-r--r-- | fusesoc.conf | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/fusesoc.conf b/fusesoc.conf index e03e5a7..2437adf 100644 --- a/fusesoc.conf +++ b/fusesoc.conf @@ -1,6 +1,5 @@ -[library.rtl] -location = /work -sync-uri = /work +[library.riscv] +location = ./ +sync-uri = ./ sync-type = local auto-sync = true - |