diff options
| author | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 23:09:39 -0500 |
|---|---|---|
| committer | Joshua Yun <joshua@joshuayun.com> | 2025-03-15 23:09:39 -0500 |
| commit | 6bd9f4f7ab48576d3fda98bef915162a7436866d (patch) | |
| tree | a0af72467af1020f9e492b177e2d95ed8998d1dc /primitives/rtl | |
| parent | 59fd8c25ee1452452cb564d6fe4163b7a9394aef (diff) | |
| download | riscv-processor-6bd9f4f7ab48576d3fda98bef915162a7436866d.tar.gz | |
feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64
Diffstat (limited to 'primitives/rtl')
| -rw-r--r-- | primitives/rtl/AFFR.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/primitives/rtl/AFFR.sv b/primitives/rtl/AFFR.sv index 012717d..0be8444 100644 --- a/primitives/rtl/AFFR.sv +++ b/primitives/rtl/AFFR.sv @@ -1,8 +1,8 @@ // AFFR # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() , .rst_l ); module AFFR #( - parameter WIDTH = 1, - parameter type DTYPE = logic [WIDTH-1:0], + parameter WIDTH = 1, + parameter type DTYPE = logic [WIDTH-1:0], parameter logic [$bits(DTYPE)-1:0] RST_VALUE = '0 ) ( |