feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete

3 files changed, 57 insertions, 0 deletions

diff --git a/primitives/primitives.core b/primitives/primitives.core
new file mode 100644
index 0000000..72a19d7
--- /dev/null
+++ b/primitives/primitives.core
@@ -0,0 +1,16 @@
+CAPI=2:
+name: bingchao:riscv:primitives:1.0.0
+description: "RTL Primitives for the RISC-V Processor"
+
+filesets:
+  rtl:
+    files:
+      - rtl/AFF.sv
+      - rtl/AFFR.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+    toplevel: top
diff --git a/primitives/rtl/AFF.sv b/primitives/rtl/AFF.sv
new file mode 100644
index 0000000..15789bf
--- /dev/null
+++ b/primitives/rtl/AFF.sv
@@ -0,0 +1,19 @@
+// AFF # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() );
+module AFF
+#(
+  parameter      WIDTH = 1,
+  parameter type DTYPE = logic [WIDTH-1:0]
+)
+(
+  input  logic clk,
+  input  logic en,
+
+  input  DTYPE d,
+  output DTYPE q
+);
+
+always_ff @(posedge clk) begin
+  if (en) q <= d;
+end
+
+endmodule
diff --git a/primitives/rtl/AFFR.sv b/primitives/rtl/AFFR.sv
new file mode 100644
index 0000000..012717d
--- /dev/null
+++ b/primitives/rtl/AFFR.sv
@@ -0,0 +1,22 @@
+// AFFR # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() , .rst_l );
+module AFFR
+#(
+  parameter                         WIDTH      = 1,
+  parameter type                    DTYPE      = logic [WIDTH-1:0],
+  parameter logic [$bits(DTYPE)-1:0] RST_VALUE = '0
+)
+(
+  input  logic clk,
+  input  logic en,
+  input  logic rst_l,
+
+  input  DTYPE d,
+  output DTYPE q
+);
+
+always_ff @(posedge clk) begin
+  if      (~rst_l)  q <= DTYPE'(RST_VALUE);
+  else if (en)      q <= d;
+end
+
+endmodule