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| author | Joshua Yun <joshua@joshuayun.com> | 2025-02-17 21:39:47 +0000 |
|---|---|---|
| committer | Joshua Yun <joshua@joshuayun.com> | 2025-02-17 21:39:47 +0000 |
| commit | bbe63db4eb09b3a010f5e64907171e1706504a61 (patch) | |
| tree | 7523bb2e38a71c37c9ed8b72a2d8639073f651ef /rtl/top.sv | |
| parent | 5c1a3bd1141706a75bd2bf26ea6315d368ca3399 (diff) | |
| parent | 8b76fdcbe6caf045925d2a0b4096fbabe881730d (diff) | |
| download | riscv-processor-bbe63db4eb09b3a010f5e64907171e1706504a61.tar.gz | |
chore: Merge branch 'joshua/fusesoc' into 'main'
Joshua/fusesoc
See merge request falsestatement/riscv_linux!4
Diffstat (limited to 'rtl/top.sv')
| -rw-r--r-- | rtl/top.sv | 0 |
1 files changed, 0 insertions, 0 deletions
diff --git a/rtl/top.sv b/rtl/top.sv new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/rtl/top.sv |