diff options
| -rw-r--r-- | README.md | 2 | ||||
| -rw-r--r-- | core/cpu.core (renamed from top.core) | 14 | ||||
| -rw-r--r-- | core/rtl/core.sv | 22 | ||||
| -rw-r--r-- | core/rtl/fetch.sv | 20 | ||||
| -rw-r--r-- | core/tb/core_tb.sv | 37 | ||||
| -rw-r--r-- | core/tb/core_tb_imem.sv | 36 | ||||
| -rw-r--r-- | fusesoc.conf | 7 | ||||
| -rw-r--r-- | primitives/primitives.core | 16 | ||||
| -rw-r--r-- | primitives/rtl/AFF.sv | 19 | ||||
| -rw-r--r-- | primitives/rtl/AFFR.sv | 22 | ||||
| -rw-r--r-- | rtl/top.sv | 0 | ||||
| -rw-r--r-- | tb/top_tb.sv | 7 |
12 files changed, 186 insertions, 16 deletions
@@ -1 +1,3 @@ # RISCV_Linux + +Building a project with fusesoc @@ -1,16 +1,20 @@ CAPI=2: -name: riscv:cpu:top:1.0.0 -description: Top level module for RISC-V processor +name: bingchao:riscv:cpu:1.0.0 +description: "RISC-V Core" filesets: rtl: files: - - rtl/top.sv + - rtl/core.sv + - rtl/fetch.sv file_type: systemVerilogSource + depend: + - bingchao:riscv:primitives tb: files: - - tb/top_tb.sv + - tb/core_tb.sv + - tb/core_tb_imem.sv file_type: systemVerilogSource targets: @@ -25,7 +29,7 @@ targets: default_tool: verilator filesets_append: - tb - toplevel: top_tb + toplevel: core_tb tools: verilator: mode: binary diff --git a/core/rtl/core.sv b/core/rtl/core.sv new file mode 100644 index 0000000..5f64e7a --- /dev/null +++ b/core/rtl/core.sv @@ -0,0 +1,22 @@ +module core +( + input logic clk, + input logic rst_l, + // Instruction mem interface + output logic [63:0] if_imem_addr_IF, + input logic [63:0] imem_id_instr_ID + + // Data mem interface +); + +fetch fetch0 ( + .clk(clk), + .rst_l(rst_l), + .if_imem_addr_IF(if_imem_addr_IF) +); + +always @ (posedge clk) begin + $display("Instruction: %x", imem_id_instr_ID); +end + +endmodule diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv new file mode 100644 index 0000000..7cbff6a --- /dev/null +++ b/core/rtl/fetch.sv @@ -0,0 +1,20 @@ +module fetch +( + input logic clk, + input logic rst_l, + + // IMEM interface + output logic [63:0] if_imem_addr_IF +); + +logic [63:0] pc_IF; +logic [63:0] pcNxt_IF; + +assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, truncate addresses to be 64 bit aligned? + +// Program Counter (PC) +assign pcNxt_IF = pc_IF + 64'd4; + +AFFR #(.WIDTH(64)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) ); + +endmodule diff --git a/core/tb/core_tb.sv b/core/tb/core_tb.sv new file mode 100644 index 0000000..9780df8 --- /dev/null +++ b/core/tb/core_tb.sv @@ -0,0 +1,37 @@ +module core_tb (); + +logic clk; +logic rst_l; + +logic [63:0] if_imem_addr_IF; +logic [63:0] imem_id_instr_ID; + +// Clock Generation +initial begin + repeat(1000) begin + clk = ~clk; + #1; + end + $finish(); +end + +initial begin + rst_l = 1'b0; + repeat (5) @(posedge clk); + rst_l = 1'b1; +end + +core_tb_imem #( .ADDR_WIDTH(16) ) imem0 ( + .clk(clk), + .if_imem_addr_IF(if_imem_addr_IF), + .imem_id_instr_ID(imem_id_instr_ID) +); + +core core0 ( + .clk(clk), + .rst_l(rst_l), + .if_imem_addr_IF(if_imem_addr_IF), + .imem_id_instr_ID(imem_id_instr_ID) +); + +endmodule diff --git a/core/tb/core_tb_imem.sv b/core/tb/core_tb_imem.sv new file mode 100644 index 0000000..e66af29 --- /dev/null +++ b/core/tb/core_tb_imem.sv @@ -0,0 +1,36 @@ +module core_tb_imem +#( + parameter ADDR_WIDTH = 64 +) +( + input logic clk, + + // Fetch Interface + input logic [63:0] if_imem_addr_IF, + + // Decode Interface + output logic [63:0] imem_id_instr_ID +); + +int assembly_file; +int status_file; +int error_file; +string error_message_file; + +logic [63:0] imem [(1<<(ADDR_WIDTH))-1:0]; + +initial begin + assembly_file = $fopen("/home/joshua/Personal/riscv_linux/core/tb/riscv_arithmetic_basic_test_0.bin", "rb"); + status_file = $fread( imem, assembly_file ); + if (status_file == 0) begin + $ferror( assembly_file, error_message_file ); + $error("File I/O Error %s", error_message_file); + end + $display("Memory Contents Initialized"); +end + +always_ff @ (posedge clk) begin + imem_id_instr_ID <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]]; +end + +endmodule diff --git a/fusesoc.conf b/fusesoc.conf index e03e5a7..2437adf 100644 --- a/fusesoc.conf +++ b/fusesoc.conf @@ -1,6 +1,5 @@ -[library.rtl] -location = /work -sync-uri = /work +[library.riscv] +location = ./ +sync-uri = ./ sync-type = local auto-sync = true - diff --git a/primitives/primitives.core b/primitives/primitives.core new file mode 100644 index 0000000..72a19d7 --- /dev/null +++ b/primitives/primitives.core @@ -0,0 +1,16 @@ +CAPI=2: +name: bingchao:riscv:primitives:1.0.0 +description: "RTL Primitives for the RISC-V Processor" + +filesets: + rtl: + files: + - rtl/AFF.sv + - rtl/AFFR.sv + file_type: systemVerilogSource + +targets: + default: &default + filesets: + - rtl + toplevel: top diff --git a/primitives/rtl/AFF.sv b/primitives/rtl/AFF.sv new file mode 100644 index 0000000..15789bf --- /dev/null +++ b/primitives/rtl/AFF.sv @@ -0,0 +1,19 @@ +// AFF # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() ); +module AFF +#( + parameter WIDTH = 1, + parameter type DTYPE = logic [WIDTH-1:0] +) +( + input logic clk, + input logic en, + + input DTYPE d, + output DTYPE q +); + +always_ff @(posedge clk) begin + if (en) q <= d; +end + +endmodule diff --git a/primitives/rtl/AFFR.sv b/primitives/rtl/AFFR.sv new file mode 100644 index 0000000..012717d --- /dev/null +++ b/primitives/rtl/AFFR.sv @@ -0,0 +1,22 @@ +// AFFR # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() , .rst_l ); +module AFFR +#( + parameter WIDTH = 1, + parameter type DTYPE = logic [WIDTH-1:0], + parameter logic [$bits(DTYPE)-1:0] RST_VALUE = '0 +) +( + input logic clk, + input logic en, + input logic rst_l, + + input DTYPE d, + output DTYPE q +); + +always_ff @(posedge clk) begin + if (~rst_l) q <= DTYPE'(RST_VALUE); + else if (en) q <= d; +end + +endmodule diff --git a/rtl/top.sv b/rtl/top.sv deleted file mode 100644 index e69de29..0000000 --- a/rtl/top.sv +++ /dev/null diff --git a/tb/top_tb.sv b/tb/top_tb.sv deleted file mode 100644 index 7643fbe..0000000 --- a/tb/top_tb.sv +++ /dev/null @@ -1,7 +0,0 @@ -module top_tb (); - -initial begin - $display("Hello World"); -end - -endmodule |