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-rw-r--r--core/cpu.core3
1 files changed, 3 insertions, 0 deletions
diff --git a/core/cpu.core b/core/cpu.core
index 7f7b499..a4e99b4 100644
--- a/core/cpu.core
+++ b/core/cpu.core
@@ -5,8 +5,10 @@ description: "RISC-V Core"
filesets:
rtl:
files:
+ - pkg/riscv_types.sv
- rtl/core.sv
- rtl/fetch.sv
+ - rtl/decode.sv
file_type: systemVerilogSource
depend:
- bingchao:riscv:primitives
@@ -33,3 +35,4 @@ targets:
tools:
verilator:
mode: binary
+ verilator_options: [--trace-fst]