5 files changed, 150 insertions, 0 deletions
diff --git a/core/cpu.core b/core/cpu.core
new file mode 100644
index 0000000..7f7b499
--- /dev/null
+++ b/core/cpu.core
@@ -0,0 +1,35 @@
+CAPI=2:
+name: bingchao:riscv:cpu:1.0.0
+description: "RISC-V Core"
+
+filesets:
+  rtl:
+    files:
+      - rtl/core.sv
+      - rtl/fetch.sv
+    file_type: systemVerilogSource
+    depend:
+      - bingchao:riscv:primitives
+
+  tb:
+    files:
+      - tb/core_tb.sv
+      - tb/core_tb_imem.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+    toplevel: top
+
+  sim:
+    <<: *default
+    description: Run top level testbench
+    default_tool: verilator
+    filesets_append:
+      - tb
+    toplevel: core_tb
+    tools:
+      verilator:
+        mode: binary
diff --git a/core/rtl/core.sv b/core/rtl/core.sv
new file mode 100644
index 0000000..5f64e7a
--- /dev/null
+++ b/core/rtl/core.sv
@@ -0,0 +1,22 @@
+module core
+(
+  input  logic clk,
+  input  logic rst_l,
+  // Instruction mem interface
+  output logic [63:0] if_imem_addr_IF,
+  input  logic [63:0] imem_id_instr_ID
+
+  // Data mem interface 
+);
+
+fetch fetch0 (
+  .clk(clk),
+  .rst_l(rst_l),
+  .if_imem_addr_IF(if_imem_addr_IF)
+);
+
+always @ (posedge clk) begin
+  $display("Instruction: %x", imem_id_instr_ID);
+end
+
+endmodule
diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv
new file mode 100644
index 0000000..7cbff6a
--- /dev/null
+++ b/core/rtl/fetch.sv
@@ -0,0 +1,20 @@
+module fetch
+(
+  input  logic clk,
+  input  logic rst_l,
+
+  // IMEM interface
+  output logic [63:0] if_imem_addr_IF
+);
+
+logic [63:0] pc_IF;
+logic [63:0] pcNxt_IF;
+
+assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, truncate addresses to be 64 bit aligned?
+
+// Program Counter (PC)
+assign pcNxt_IF = pc_IF + 64'd4;
+
+AFFR #(.WIDTH(64)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) );
+
+endmodule
diff --git a/core/tb/core_tb.sv b/core/tb/core_tb.sv
new file mode 100644
index 0000000..9780df8
--- /dev/null
+++ b/core/tb/core_tb.sv
@@ -0,0 +1,37 @@
+module core_tb ();
+
+logic clk;
+logic rst_l;
+
+logic [63:0] if_imem_addr_IF;
+logic [63:0] imem_id_instr_ID;
+
+// Clock Generation
+initial begin
+  repeat(1000) begin
+    clk = ~clk;
+    #1;
+  end
+  $finish();
+end
+
+initial begin
+  rst_l = 1'b0;
+  repeat (5) @(posedge clk);
+  rst_l = 1'b1;
+end
+
+core_tb_imem #( .ADDR_WIDTH(16) ) imem0 (
+  .clk(clk),
+  .if_imem_addr_IF(if_imem_addr_IF),
+  .imem_id_instr_ID(imem_id_instr_ID)
+);
+
+core core0 (
+  .clk(clk),
+  .rst_l(rst_l),
+  .if_imem_addr_IF(if_imem_addr_IF),
+  .imem_id_instr_ID(imem_id_instr_ID)
+);
+
+endmodule
diff --git a/core/tb/core_tb_imem.sv b/core/tb/core_tb_imem.sv
new file mode 100644
index 0000000..e66af29
--- /dev/null
+++ b/core/tb/core_tb_imem.sv
@@ -0,0 +1,36 @@
+module core_tb_imem
+#(
+  parameter ADDR_WIDTH = 64
+)
+(
+  input  logic        clk,
+
+  // Fetch Interface
+  input  logic [63:0] if_imem_addr_IF,
+
+  // Decode Interface
+  output logic [63:0] imem_id_instr_ID
+);
+
+int assembly_file;
+int status_file;
+int error_file;
+string error_message_file;
+
+logic [63:0] imem [(1<<(ADDR_WIDTH))-1:0];
+
+initial begin
+  assembly_file = $fopen("/home/joshua/Personal/riscv_linux/core/tb/riscv_arithmetic_basic_test_0.bin", "rb");
+  status_file   = $fread( imem, assembly_file );
+  if (status_file == 0) begin
+    $ferror( assembly_file, error_message_file );
+    $error("File I/O Error %s", error_message_file);
+  end
+  $display("Memory Contents Initialized");
+end
+
+always_ff @ (posedge clk) begin
+  imem_id_instr_ID <= imem[if_imem_addr_IF[ADDR_WIDTH-1:0]];
+end
+
+endmodule