1 files changed, 39 insertions, 0 deletions
diff --git a/top.core b/top.core
new file mode 100644
index 0000000..e8a009d
--- /dev/null
+++ b/top.core
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+CAPI=2:
+name: bingchao:riscv:top
+description: Fully Linux Capable Processor
+
+filesets:
+  rtl:
+    files:
+      - rtl/top.sv
+      - rtl/top.svh:
+          is_include_file: true
+    file_type: systemVerilogSource
+
+  tb:
+    files:
+      - tb/top_tb.sv
+    file_type: systemVerilogSource
+
+targets:
+
+  default: &default
+    filesets:
+      - rtl
+    toplevel: top
+    parameters:
+      - clk_freq_hz
+
+    sim:
+      <<: *default
+      description: Simulate the design
+      default_tool: verilator
+      tools:
+        verilator:
+          verilator_options:
+        icarus:
+          iverilog_options:
+            - -g2012
+      parameters:
+        - pulses=10
+