diff options
Diffstat (limited to 'top.core')
| -rw-r--r-- | top.core | 32 |
1 files changed, 12 insertions, 20 deletions
@@ -1,13 +1,11 @@ CAPI=2: -name: bingchao:riscv:top -description: Fully Linux Capable Processor +name: riscv:cpu:top:1.0.0 +description: Top level module for RISC-V processor filesets: rtl: files: - rtl/top.sv - - rtl/top.svh: - is_include_file: true file_type: systemVerilogSource tb: @@ -16,24 +14,18 @@ filesets: file_type: systemVerilogSource targets: - default: &default filesets: - rtl toplevel: top - parameters: - - clk_freq_hz - - sim: - <<: *default - description: Simulate the design - default_tool: verilator - tools: - verilator: - verilator_options: - icarus: - iverilog_options: - - -g2012 - parameters: - - pulses=10 + sim: + <<: *default + description: Run top level testbench + default_tool: verilator + filesets_append: + - tb + toplevel: top_tb + tools: + verilator: + mode: binary |