| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | fix: permissions fixjoshua/core | Joshua Yun | 2025-05-22 | 5 | -0/+0 |
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| * | finished exe stage | Joshua Yun | 2025-05-22 | 7 | -155/+267 |
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| * | initial commit | Joshua Yun | 2025-05-17 | 7 | -175/+410 |
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| * | feat: initial completion of decode stage, fix: removed hardcoded path for ↵ | Joshua Yun | 2025-03-25 | 6 | -18/+11891 |
| | | | | | riscv assembly files in TB | ||||
| * | feat: More setting up, got a janky decode stage that prints out the ↵ | Joshua Yun | 2025-03-15 | 8 | -27/+102 |
| | | | | | instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64 | ||||
| * | feat: added TB support + primitives for flipflops, initial fetch stage (not ↵ | Joshua Yun | 2025-03-15 | 5 | -0/+150 |
| complete), mem initialization for imem complete | |||||
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index : riscv-processor | |
| RISC-V Processor | joshua |
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