| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | feat: More setting up, got a janky decode stage that prints out the ↵ | Joshua Yun | 2025-03-15 | 1 | -2/+2 |
| | | | | | instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64 | ||||
| * | feat: added TB support + primitives for flipflops, initial fetch stage (not ↵ | Joshua Yun | 2025-03-15 | 1 | -0/+22 |
| complete), mem initialization for imem complete | |||||
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index : riscv-processor | |
| RISC-V Processor | joshua |
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