riscv-processor - RISC-V Processor

	Commit message (Collapse)	Author	Age	Files	Lines
*	fix: permissions fixjoshua/core	Joshua Yun	2025-05-22	4	-0/+0
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*	finished exe stage	Joshua Yun	2025-05-22	4	-0/+0
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*	initial commit	Joshua Yun	2025-05-17	2	-0/+16
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*	feat: More setting up, got a janky decode stage that prints out the ↵	Joshua Yun	2025-03-15	1	-2/+2
\| \| \| \|	instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64
*	feat: added TB support + primitives for flipflops, initial fetch stage (not ↵	Joshua Yun	2025-03-15	2	-0/+41
	complete), mem initialization for imem complete