From 59fd8c25ee1452452cb564d6fe4163b7a9394aef Mon Sep 17 00:00:00 2001
From: Joshua Yun <joshua@joshuayun.com>
Date: Sat, 15 Mar 2025 17:35:52 -0500
Subject: feat: added TB support + primitives for flipflops, initial fetch
 stage (not complete), mem initialization for imem complete

---
 core/cpu.core | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 core/cpu.core

(limited to 'core/cpu.core')

diff --git a/core/cpu.core b/core/cpu.core
new file mode 100644
index 0000000..7f7b499
--- /dev/null
+++ b/core/cpu.core
@@ -0,0 +1,35 @@
+CAPI=2:
+name: bingchao:riscv:cpu:1.0.0
+description: "RISC-V Core"
+
+filesets:
+  rtl:
+    files:
+      - rtl/core.sv
+      - rtl/fetch.sv
+    file_type: systemVerilogSource
+    depend:
+      - bingchao:riscv:primitives
+
+  tb:
+    files:
+      - tb/core_tb.sv
+      - tb/core_tb_imem.sv
+    file_type: systemVerilogSource
+
+targets:
+  default: &default
+    filesets:
+      - rtl
+    toplevel: top
+
+  sim:
+    <<: *default
+    description: Run top level testbench
+    default_tool: verilator
+    filesets_append:
+      - tb
+    toplevel: core_tb
+    tools:
+      verilator:
+        mode: binary
-- 
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