From 6bd9f4f7ab48576d3fda98bef915162a7436866d Mon Sep 17 00:00:00 2001
From: Joshua Yun <joshua@joshuayun.com>
Date: Sat, 15 Mar 2025 23:09:39 -0500
Subject: feat: More setting up, got a janky decode stage that prints out the
 instruction it receives, added dump options to fusesoc, changed instr width
 back th 32 from 64

---
 core/cpu.core | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'core/cpu.core')

diff --git a/core/cpu.core b/core/cpu.core
index 7f7b499..a4e99b4 100644
--- a/core/cpu.core
+++ b/core/cpu.core
@@ -5,8 +5,10 @@ description: "RISC-V Core"
 filesets:
   rtl:
     files:
+      - pkg/riscv_types.sv
       - rtl/core.sv
       - rtl/fetch.sv
+      - rtl/decode.sv
     file_type: systemVerilogSource
     depend:
       - bingchao:riscv:primitives
@@ -33,3 +35,4 @@ targets:
     tools:
       verilator:
         mode: binary
+        verilator_options: [--trace-fst]
-- 
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