From 86021b3616c24efe38d8869b45d201bf24fe9a07 Mon Sep 17 00:00:00 2001
From: Joshua Yun <joshua@joshuayun.com>
Date: Tue, 25 Mar 2025 00:29:30 -0500
Subject: feat: initial completion of decode stage, fix: removed hardcoded path
 for riscv assembly files in TB

---
 core/pkg/riscv_types.sv | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'core/pkg')

diff --git a/core/pkg/riscv_types.sv b/core/pkg/riscv_types.sv
index 3d68331..48ca87b 100644
--- a/core/pkg/riscv_types.sv
+++ b/core/pkg/riscv_types.sv
@@ -11,4 +11,28 @@ package riscv_types;
       INSTR_TYPE_REG   = 7'b0110011, // R arith ops with register operands 
       INSTR_TYPE_CSR   = 7'b1110011  // I control and status register
   } opcode_t;
+
+  typedef enum logic [1:0] {
+    MEM_OP_LOAD,
+    MEM_OP_STORE,
+    MEM_OP_NONE
+  } mem_op_t;
+
+  typedef enum logic [1:0] {
+    REG_IMM_OFFSET,
+    PC_IMM_OFFSET,
+    OFFSET_NONE
+  } brjmp_op_t;
+
+  typedef enum logic [1:0] {
+    RS1,
+    PC,
+    OP_NONE
+  } aluSelOp1_t;
+
+  typedef enum logic {
+    RS2,
+    IMM
+  } aluSelOp2_t;
+
 endpackage
-- 
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