From 59fd8c25ee1452452cb564d6fe4163b7a9394aef Mon Sep 17 00:00:00 2001
From: Joshua Yun <joshua@joshuayun.com>
Date: Sat, 15 Mar 2025 17:35:52 -0500
Subject: feat: added TB support + primitives for flipflops, initial fetch
 stage (not complete), mem initialization for imem complete

---
 core/rtl/core.sv | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 core/rtl/core.sv

(limited to 'core/rtl/core.sv')

diff --git a/core/rtl/core.sv b/core/rtl/core.sv
new file mode 100644
index 0000000..5f64e7a
--- /dev/null
+++ b/core/rtl/core.sv
@@ -0,0 +1,22 @@
+module core
+(
+  input  logic clk,
+  input  logic rst_l,
+  // Instruction mem interface
+  output logic [63:0] if_imem_addr_IF,
+  input  logic [63:0] imem_id_instr_ID
+
+  // Data mem interface 
+);
+
+fetch fetch0 (
+  .clk(clk),
+  .rst_l(rst_l),
+  .if_imem_addr_IF(if_imem_addr_IF)
+);
+
+always @ (posedge clk) begin
+  $display("Instruction: %x", imem_id_instr_ID);
+end
+
+endmodule
-- 
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