From 6bd9f4f7ab48576d3fda98bef915162a7436866d Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Sat, 15 Mar 2025 23:09:39 -0500 Subject: feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64 --- core/rtl/core.sv | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'core/rtl/core.sv') diff --git a/core/rtl/core.sv b/core/rtl/core.sv index 5f64e7a..d9a51dd 100644 --- a/core/rtl/core.sv +++ b/core/rtl/core.sv @@ -1,10 +1,11 @@ module core +import riscv_types::*; ( input logic clk, input logic rst_l, // Instruction mem interface - output logic [63:0] if_imem_addr_IF, - input logic [63:0] imem_id_instr_ID + output logic [31:0] if_imem_addr_IF, + input logic [31:0] imem_id_instr_ID // Data mem interface ); @@ -15,8 +16,10 @@ fetch fetch0 ( .if_imem_addr_IF(if_imem_addr_IF) ); -always @ (posedge clk) begin - $display("Instruction: %x", imem_id_instr_ID); -end +decode decode0 ( + .clk(clk), + .rst_l(rst_l), + .imem_id_instr_ID(imem_id_instr_ID) +); endmodule -- cgit v1.2.3