From 59fd8c25ee1452452cb564d6fe4163b7a9394aef Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Sat, 15 Mar 2025 17:35:52 -0500 Subject: feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete --- core/rtl/fetch.sv | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 core/rtl/fetch.sv (limited to 'core/rtl/fetch.sv') diff --git a/core/rtl/fetch.sv b/core/rtl/fetch.sv new file mode 100644 index 0000000..7cbff6a --- /dev/null +++ b/core/rtl/fetch.sv @@ -0,0 +1,20 @@ +module fetch +( + input logic clk, + input logic rst_l, + + // IMEM interface + output logic [63:0] if_imem_addr_IF +); + +logic [63:0] pc_IF; +logic [63:0] pcNxt_IF; + +assign if_imem_addr_IF = pc_IF; // Always fetch PC from IMEM, truncate addresses to be 64 bit aligned? + +// Program Counter (PC) +assign pcNxt_IF = pc_IF + 64'd4; + +AFFR #(.WIDTH(64)) ff_IF_pc ( .clk(clk), .rst_l(rst_l), .en(1'b1), .q(pc_IF), .d(pcNxt_IF) ); + +endmodule -- cgit v1.2.3