From 6bd9f4f7ab48576d3fda98bef915162a7436866d Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Sat, 15 Mar 2025 23:09:39 -0500 Subject: feat: More setting up, got a janky decode stage that prints out the instruction it receives, added dump options to fusesoc, changed instr width back th 32 from 64 --- primitives/rtl/AFFR.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'primitives/rtl/AFFR.sv') diff --git a/primitives/rtl/AFFR.sv b/primitives/rtl/AFFR.sv index 012717d..0be8444 100644 --- a/primitives/rtl/AFFR.sv +++ b/primitives/rtl/AFFR.sv @@ -1,8 +1,8 @@ // AFFR # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() , .rst_l ); module AFFR #( - parameter WIDTH = 1, - parameter type DTYPE = logic [WIDTH-1:0], + parameter WIDTH = 1, + parameter type DTYPE = logic [WIDTH-1:0], parameter logic [$bits(DTYPE)-1:0] RST_VALUE = '0 ) ( -- cgit v1.2.3