From 59fd8c25ee1452452cb564d6fe4163b7a9394aef Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Sat, 15 Mar 2025 17:35:52 -0500 Subject: feat: added TB support + primitives for flipflops, initial fetch stage (not complete), mem initialization for imem complete --- top.core | 31 ------------------------------- 1 file changed, 31 deletions(-) delete mode 100644 top.core (limited to 'top.core') diff --git a/top.core b/top.core deleted file mode 100644 index db67ab4..0000000 --- a/top.core +++ /dev/null @@ -1,31 +0,0 @@ -CAPI=2: -name: riscv:cpu:top:1.0.0 -description: Top level module for RISC-V processor - -filesets: - rtl: - files: - - rtl/top.sv - file_type: systemVerilogSource - - tb: - files: - - tb/top_tb.sv - file_type: systemVerilogSource - -targets: - default: &default - filesets: - - rtl - toplevel: top - - sim: - <<: *default - description: Run top level testbench - default_tool: verilator - filesets_append: - - tb - toplevel: top_tb - tools: - verilator: - mode: binary -- cgit v1.2.3