From 7cb6c29fde2543dff50987964d03f2525376a429 Mon Sep 17 00:00:00 2001 From: Joshua Yun Date: Sun, 16 Feb 2025 15:08:05 -0600 Subject: Initial docker setup commit --- top.core | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 top.core (limited to 'top.core') diff --git a/top.core b/top.core new file mode 100644 index 0000000..e8a009d --- /dev/null +++ b/top.core @@ -0,0 +1,39 @@ +CAPI=2: +name: bingchao:riscv:top +description: Fully Linux Capable Processor + +filesets: + rtl: + files: + - rtl/top.sv + - rtl/top.svh: + is_include_file: true + file_type: systemVerilogSource + + tb: + files: + - tb/top_tb.sv + file_type: systemVerilogSource + +targets: + + default: &default + filesets: + - rtl + toplevel: top + parameters: + - clk_freq_hz + + sim: + <<: *default + description: Simulate the design + default_tool: verilator + tools: + verilator: + verilator_options: + icarus: + iverilog_options: + - -g2012 + parameters: + - pulses=10 + -- cgit v1.2.3