From 8b76fdcbe6caf045925d2a0b4096fbabe881730d Mon Sep 17 00:00:00 2001
From: Joshua Yun <joshua@joshuayun.com>
Date: Mon, 17 Feb 2025 21:39:47 +0000
Subject: Joshua/fusesoc

---
 top.core | 32 ++++++++++++--------------------
 1 file changed, 12 insertions(+), 20 deletions(-)

(limited to 'top.core')

diff --git a/top.core b/top.core
index e8a009d..db67ab4 100644
--- a/top.core
+++ b/top.core
@@ -1,13 +1,11 @@
 CAPI=2:
-name: bingchao:riscv:top
-description: Fully Linux Capable Processor
+name: riscv:cpu:top:1.0.0
+description: Top level module for RISC-V processor
 
 filesets:
   rtl:
     files:
       - rtl/top.sv
-      - rtl/top.svh:
-          is_include_file: true
     file_type: systemVerilogSource
 
   tb:
@@ -16,24 +14,18 @@ filesets:
     file_type: systemVerilogSource
 
 targets:
-
   default: &default
     filesets:
       - rtl
     toplevel: top
-    parameters:
-      - clk_freq_hz
-
-    sim:
-      <<: *default
-      description: Simulate the design
-      default_tool: verilator
-      tools:
-        verilator:
-          verilator_options:
-        icarus:
-          iverilog_options:
-            - -g2012
-      parameters:
-        - pulses=10
 
+  sim:
+    <<: *default
+    description: Run top level testbench
+    default_tool: verilator
+    filesets_append:
+      - tb
+    toplevel: top_tb
+    tools:
+      verilator:
+        mode: binary
-- 
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