module core_tb 
#(
  parameter TIMEOUT    = 10,
  parameter ADDR_WIDTH = 16
);

logic clk;
logic rst_l;

// imem instruction interface
logic [31:0] if_imem_addr_IF;
logic [31:0] imem_id_instr_ID;

// Clock Generation
always begin
  clk = #1 ~clk;
end

// Signal Dump, Test Timeout, and Reset
initial begin
  // Dump Setup
  $dumpfile("dump.fst");
  $dumpvars;

  // Reset Set up
  rst_l = 1'b0;
  repeat (5) @(posedge clk);
  rst_l = 1'b1;

  // Timeout Setup
  repeat (TIMEOUT) @(posedge clk);
  $finish("Test Timed Out"); // TODO Make error & increase timeout length
end

core_tb_imem #( .ADDR_WIDTH(ADDR_WIDTH) ) imem0 (
  .clk(clk),
  .if_imem_addr_IF(if_imem_addr_IF),
  .imem_id_instr_ID(imem_id_instr_ID)
);

core core0 (
  .clk(clk),
  .rst_l(rst_l),
  .if_imem_addr_IF(if_imem_addr_IF),
  .imem_id_instr_ID(imem_id_instr_ID)
);

endmodule