SHELL = /bin/bash -o pipefail

TOP_TB_SRCS   := $(PWD)/hvl/tb_top.sv   $(PWD)/hdl/multiplier.sv  $(PWD)/hdl/sm.sv  $(PWD)/hdl/ff_array.sv


export REPORT_DIR			= reports
export SYN_OUT_DIR			= ./syn/synout

VCS_FLAGS= -full64 -lca -sverilog +lint=none,noNS -timescale=1ns/1ns -debug_acc+all -kdb -fsdb -j4 +notimingcheck
VCS_FLAGS_POST = -full64 -lca -sverilog +lint=none -timescale=1ns/1ns -debug_acc+all -kdb -fsdb +neg_tchk -negdelay +compsdf +mindelays +sdfverbose -j4 -fgp

tree:
	./gen_wallace.py 32 -a

sim/top_tb: $(TOP_TB_SRCS)
	mkdir -p sim
	cd sim && vcs $(TOP_TB_SRCS) $(VCS_FLAGS) -l top_compile.log -o top_tb
	cd sim && ./top_tb -l top_simulation.log

synth: synth_clean
	mkdir -p $(REPORT_DIR) $(SYN_OUT_DIR)
	dc_shell-xg-t -64bit -f dc_syn.tcl |& tee $(REPORT_DIR)/synthesis.log
	$(MAKE) smol_clean

.PHONY: verdi 
verdi:
	mkdir -p verdi
	cd verdi && $(VERDI_HOME)/bin/verdi -ssf $(PWD)/sim/dump.fsdb

.PHONY: synth_clean
synth_clean: smol_clean
	rm -f  synthesis.log
	rm -rf $(REPORT_DIR)
	rm -rf $(SYN_OUT_DIR)

.PHONY: smol_clean
smol_clean:
	rm -f  command.log
	rm -f  default.svf
	rm -rf work