core/cpu.core


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CAPI=2:
name: bingchao:riscv:cpu:1.0.0
description: "RISC-V Core"

filesets:
  rtl:
    files:
      - rtl/core.sv
      - rtl/fetch.sv
    file_type: systemVerilogSource
    depend:
      - bingchao:riscv:primitives

  tb:
    files:
      - tb/core_tb.sv
      - tb/core_tb_imem.sv
    file_type: systemVerilogSource

targets:
  default: &default
    filesets:
      - rtl
    toplevel: top

  sim:
    <<: *default
    description: Run top level testbench
    default_tool: verilator
    filesets_append:
      - tb
    toplevel: core_tb
    tools:
      verilator:
        mode: binary