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module core
import riscv_types::*;
(
input logic clk,
input logic rst_l,
// Instruction mem interface
output logic [31:0] if_imem_addr_IF,
input logic [31:0] imem_id_instr_ID
// Data mem interface
);
fetch fetch0 (
.clk(clk),
.rst_l(rst_l),
.if_imem_addr_IF(if_imem_addr_IF)
);
decode decode0 (
.clk(clk),
.rst_l(rst_l),
.imem_id_instr_ID(imem_id_instr_ID)
);
endmodule
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