core/rtl/decode.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

module decode
import riscv_types::*;
#(
  )
  (
    input  logic        clk,
    input  logic        rst_l,

    // I-MEM Interface
    input  logic [31:0] imem_id_instr_ID
  );

opcode_t instrOpCode_ID;

assign instrOpCode_ID = opcode_t'(imem_id_instr_ID[6:0]);

always_ff @(posedge clk) begin
  $display("Instruction: %x", imem_id_instr_ID);
  case (instrOpCode_ID)
    INSTR_TYPE_LUI:    begin $display("Instr type: LUI"); end
    INSTR_TYPE_AUIPC:  begin $display("Instr type: AUIPC"); end
    INSTR_TYPE_JAL:    begin $display("Instr type: JAL"); end
    INSTR_TYPE_JALR:   begin $display("Instr type: JALR"); end
    INSTR_TYPE_BR:     begin $display("Instr type: BR"); end
    INSTR_TYPE_LD:     begin $display("Instr type: LD"); end
    INSTR_TYPE_ST:     begin $display("Instr type: ST"); end
    INSTR_TYPE_IMM:    begin $display("Instr type: IMM"); end
    INSTR_TYPE_REG:    begin $display("Instr type: REG"); end
    INSTR_TYPE_CSR:    begin $display("Instr type: CSR"); end
    default:           begin $display("Instr type: Unknown"); end
  endcase
end

endmodule