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// AFFR # ( .WIDTH/.DTYPE() ) ff_ ( .q(), .d(), .en(), .clk() , .rst_l );
module AFFR
#(
parameter WIDTH = 1,
parameter type DTYPE = logic [WIDTH-1:0],
parameter logic [$bits(DTYPE)-1:0] RST_VALUE = '0
)
(
input logic clk,
input logic en,
input logic rst_l,
input DTYPE d,
output DTYPE q
);
always_ff @(posedge clk) begin
if (~rst_l) q <= DTYPE'(RST_VALUE);
else if (en) q <= d;
end
endmodule
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