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CAPI=2:
name: riscv:cpu:top:1.0.0
description: Top level module for RISC-V processor
filesets:
rtl:
files:
- rtl/top.sv
file_type: systemVerilogSource
tb:
files:
- tb/top_tb.sv
file_type: systemVerilogSource
targets:
default: &default
filesets:
- rtl
toplevel: top
sim:
<<: *default
description: Run top level testbench
default_tool: verilator
filesets_append:
- tb
toplevel: top_tb
tools:
verilator:
mode: binary
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