diff options
Diffstat (limited to 'Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example')
12 files changed, 1706 insertions, 0 deletions
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt new file mode 100644 index 0000000..f45b0e0 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_matrix_example for
+ Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU.
+
+The example is configured for uVision Simulator.
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..bdb4be7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//**
+; * @file startup_ARMCM0.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Heap_Size EQU 0x00000C00
+
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+ ENDIF
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+; User setup Stack & Heap
+
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
+ ENDIF
+
+ END
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..d735adf --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//**
+ * @file system_ARMCM0.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM0 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..81a33d9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//**
+; * @file startup_ARMCM3.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Heap_Size EQU 0x00000C00
+
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+ ENDIF
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+; User setup Stack & Heap
+
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
+ ENDIF
+
+ END
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..5578e23 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..93f7f27 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//**
+; * @file startup_ARMCM4.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Heap_Size EQU 0x00000C00
+
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+ ENDIF
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+; User setup Stack & Heap
+
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
+ ENDIF
+
+ END
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..cfac6b2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//**
+ * @file system_ARMCM4.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM4 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM4)
+ #include "ARMCM4.h"
+#elif defined (ARMCM4_FP)
+ #include "ARMCM4_FP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..f9d954a --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//**
+; * @file startup_ARMCM7.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM7 Device
+; * @version V5.3.1
+; * @date 09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+;<h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+__stack_limit
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+;<h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+Heap_Size EQU 0x00000C00
+
+ IF Heap_Size != 0 ; Heap is provided
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+ ENDIF
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; -14 NMI Handler
+ DCD HardFault_Handler ; -13 Hard Fault Handler
+ DCD MemManage_Handler ; -12 MPU Fault Handler
+ DCD BusFault_Handler ; -11 Bus Fault Handler
+ DCD UsageFault_Handler ; -10 Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; -5 SVCall Handler
+ DCD DebugMon_Handler ; -4 Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; -2 PendSV Handler
+ DCD SysTick_Handler ; -1 SysTick Handler
+
+ ; Interrupts
+ DCD Interrupt0_Handler ; 0 Interrupt 0
+ DCD Interrupt1_Handler ; 1 Interrupt 1
+ DCD Interrupt2_Handler ; 2 Interrupt 2
+ DCD Interrupt3_Handler ; 3 Interrupt 3
+ DCD Interrupt4_Handler ; 4 Interrupt 4
+ DCD Interrupt5_Handler ; 5 Interrupt 5
+ DCD Interrupt6_Handler ; 6 Interrupt 6
+ DCD Interrupt7_Handler ; 7 Interrupt 7
+ DCD Interrupt8_Handler ; 8 Interrupt 8
+ DCD Interrupt9_Handler ; 9 Interrupt 9
+
+ SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
+__Vectors_End
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+ MACRO
+ Set_Default_Handler $Handler_Name
+$Handler_Name PROC
+ EXPORT $Handler_Name [WEAK]
+ B .
+ ENDP
+ MEND
+
+
+; Default exception/interrupt handler
+
+ Set_Default_Handler NMI_Handler
+ Set_Default_Handler HardFault_Handler
+ Set_Default_Handler MemManage_Handler
+ Set_Default_Handler BusFault_Handler
+ Set_Default_Handler UsageFault_Handler
+ Set_Default_Handler SVC_Handler
+ Set_Default_Handler DebugMon_Handler
+ Set_Default_Handler PendSV_Handler
+ Set_Default_Handler SysTick_Handler
+
+ Set_Default_Handler Interrupt0_Handler
+ Set_Default_Handler Interrupt1_Handler
+ Set_Default_Handler Interrupt2_Handler
+ Set_Default_Handler Interrupt3_Handler
+ Set_Default_Handler Interrupt4_Handler
+ Set_Default_Handler Interrupt5_Handler
+ Set_Default_Handler Interrupt6_Handler
+ Set_Default_Handler Interrupt7_Handler
+ Set_Default_Handler Interrupt8_Handler
+ Set_Default_Handler Interrupt9_Handler
+
+ ALIGN
+
+
+; User setup Stack & Heap
+
+ EXPORT __stack_limit
+ EXPORT __initial_sp
+ IF Heap_Size != 0 ; Heap is provided
+ EXPORT __heap_base
+ EXPORT __heap_limit
+ ENDIF
+
+ END
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..affc835 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//**
+ * @file system_ARMCM7.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM7 Device
+ * @version V5.3.1
+ * @date 09. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined (ARMCM7)
+ #include "ARMCM7.h"
+#elif defined (ARMCM7_SP)
+ #include "ARMCM7_SP.h"
+#elif defined (ARMCM7_DP)
+ #include "ARMCM7_DP.h"
+#else
+ #error device not specified!
+#endif
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (50000000UL) /* Oscillator frequency */
+
+#define SYSTEM_CLOCK (XTAL / 2U)
+
+
+/*----------------------------------------------------------------------------
+ Externals
+ *----------------------------------------------------------------------------*/
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+#endif
+
+/*----------------------------------------------------------------------------
+ System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
+
+
+/*----------------------------------------------------------------------------
+ System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/*----------------------------------------------------------------------------
+ System initialization function
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+}
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c new file mode 100644 index 0000000..3d7a505 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c @@ -0,0 +1,233 @@ +/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+* Title: arm_matrix_example_f32.c
+*
+* Description: Example code demonstrating least square fit to data
+* using matrix functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ * @ingroup groupExamples
+ */
+
+/**
+ * @defgroup MatrixExample Matrix Example
+ *
+ * \par Description:
+ * \par
+ * Demonstrates the use of Matrix Transpose, Matrix Muliplication, and Matrix Inverse
+ * functions to apply least squares fitting to input data. Least squares fitting is
+ * the procedure for finding the best-fitting curve that minimizes the sum of the
+ * squares of the offsets (least square error) from a given set of data.
+ *
+ * \par Algorithm:
+ * \par
+ * The linear combination of parameters considered is as follows:
+ * \par
+ * <code>A * X = B</code>, where \c X is the unknown value and can be estimated
+ * from \c A & \c B.
+ * \par
+ * The least squares estimate \c X is given by the following equation:
+ * \par
+ * <code>X = Inverse(A<sup>T</sup> * A) * A<sup>T</sup> * B</code>
+ *
+ * \par Block Diagram:
+ * \par
+ * \image html matrixExample.gif
+ *
+ * \par Variables Description:
+ * \par
+ * \li \c A_f32 input matrix in the linear combination equation
+ * \li \c B_f32 output matrix in the linear combination equation
+ * \li \c X_f32 unknown matrix estimated using \c A_f32 & \c B_f32 matrices
+ *
+ * \par CMSIS DSP Software Library Functions Used:
+ * \par
+ * - arm_mat_init_f32()
+ * - arm_mat_trans_f32()
+ * - arm_mat_mult_f32()
+ * - arm_mat_inverse_f32()
+ *
+ * <b> Refer </b>
+ * \link arm_matrix_example_f32.c \endlink
+ *
+ */
+
+
+/** \example arm_matrix_example_f32.c
+ */
+
+#include "arm_math.h"
+#include "math_helper.h"
+
+#define SNR_THRESHOLD 90
+
+/* --------------------------------------------------------------------------------
+* Test input data(Cycles) taken from FIR Q15 module for differant cases of blockSize
+* and tapSize
+* --------------------------------------------------------------------------------- */
+
+const float32_t B_f32[4] =
+{
+ 782.0, 7577.0, 470.0, 4505.0
+};
+
+/* --------------------------------------------------------------------------------
+* Formula to fit is C1 + C2 * numTaps + C3 * blockSize + C4 * numTaps * blockSize
+* -------------------------------------------------------------------------------- */
+
+const float32_t A_f32[16] =
+{
+ /* Const, numTaps, blockSize, numTaps*blockSize */
+ 1.0, 32.0, 4.0, 128.0,
+ 1.0, 32.0, 64.0, 2048.0,
+ 1.0, 16.0, 4.0, 64.0,
+ 1.0, 16.0, 64.0, 1024.0,
+};
+
+
+/* ----------------------------------------------------------------------
+* Temporary buffers for storing intermediate values
+* ------------------------------------------------------------------- */
+/* Transpose of A Buffer */
+float32_t AT_f32[16];
+/* (Transpose of A * A) Buffer */
+float32_t ATMA_f32[16];
+/* Inverse(Transpose of A * A) Buffer */
+float32_t ATMAI_f32[16];
+/* Test Output Buffer */
+float32_t X_f32[4];
+
+/* ----------------------------------------------------------------------
+* Reference ouput buffer C1, C2, C3 and C4 taken from MATLAB
+* ------------------------------------------------------------------- */
+const float32_t xRef_f32[4] = {73.0, 8.0, 21.25, 2.875};
+
+float32_t snr;
+
+
+/* ----------------------------------------------------------------------
+* Max magnitude FFT Bin test
+* ------------------------------------------------------------------- */
+
+int32_t main(void)
+{
+
+ arm_matrix_instance_f32 A; /* Matrix A Instance */
+ arm_matrix_instance_f32 AT; /* Matrix AT(A transpose) instance */
+ arm_matrix_instance_f32 ATMA; /* Matrix ATMA( AT multiply with A) instance */
+ arm_matrix_instance_f32 ATMAI; /* Matrix ATMAI(Inverse of ATMA) instance */
+ arm_matrix_instance_f32 B; /* Matrix B instance */
+ arm_matrix_instance_f32 X; /* Matrix X(Unknown Matrix) instance */
+
+ uint32_t srcRows, srcColumns; /* Temporary variables */
+ arm_status status;
+
+ /* Initialise A Matrix Instance with numRows, numCols and data array(A_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&A, srcRows, srcColumns, (float32_t *)A_f32);
+
+ /* Initialise Matrix Instance AT with numRows, numCols and data array(AT_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&AT, srcRows, srcColumns, AT_f32);
+
+ /* calculation of A transpose */
+ status = arm_mat_trans_f32(&A, &AT);
+
+
+ /* Initialise ATMA Matrix Instance with numRows, numCols and data array(ATMA_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&ATMA, srcRows, srcColumns, ATMA_f32);
+
+ /* calculation of AT Multiply with A */
+ status = arm_mat_mult_f32(&AT, &A, &ATMA);
+
+ /* Initialise ATMAI Matrix Instance with numRows, numCols and data array(ATMAI_f32) */
+ srcRows = 4;
+ srcColumns = 4;
+ arm_mat_init_f32(&ATMAI, srcRows, srcColumns, ATMAI_f32);
+
+ /* calculation of Inverse((Transpose(A) * A) */
+ status = arm_mat_inverse_f32(&ATMA, &ATMAI);
+
+ /* calculation of (Inverse((Transpose(A) * A)) * Transpose(A)) */
+ status = arm_mat_mult_f32(&ATMAI, &AT, &ATMA);
+
+ /* Initialise B Matrix Instance with numRows, numCols and data array(B_f32) */
+ srcRows = 4;
+ srcColumns = 1;
+ arm_mat_init_f32(&B, srcRows, srcColumns, (float32_t *)B_f32);
+
+ /* Initialise X Matrix Instance with numRows, numCols and data array(X_f32) */
+ srcRows = 4;
+ srcColumns = 1;
+ arm_mat_init_f32(&X, srcRows, srcColumns, X_f32);
+
+ /* calculation ((Inverse((Transpose(A) * A)) * Transpose(A)) * B) */
+ status = arm_mat_mult_f32(&ATMA, &B, &X);
+
+ /* Comparison of reference with test output */
+ snr = arm_snr_f32((float32_t *)xRef_f32, X_f32, 4);
+
+ /*------------------------------------------------------------------------------
+ * Initialise status depending on SNR calculations
+ *------------------------------------------------------------------------------*/
+ if ( snr > SNR_THRESHOLD)
+ {
+ status = ARM_MATH_SUCCESS;
+ }
+ else
+ {
+ status = ARM_MATH_TEST_FAILURE;
+ }
+
+
+ /* ----------------------------------------------------------------------
+ ** Loop here if the signals fail the PASS check.
+ ** This denotes a test failure
+ ** ------------------------------------------------------------------- */
+ if ( status != ARM_MATH_SUCCESS)
+ {
+ while (1);
+ }
+
+ while (1); /* main function does not return */
+}
+
+ /** \endlink */
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c new file mode 100644 index 0000000..f615e6f --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c @@ -0,0 +1,466 @@ +/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0 b
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param[in] pRef Pointer to the reference buffer
+ * @param[in] pTest Pointer to the test buffer
+ * @param[in] buffSize total number of samples
+ * @return SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if (temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to outputbuffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param[in] pIn Pointer to Ref buffer
+ * @param[in] pOut Pointer to Test buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return maximum difference
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff, diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if (diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param[in,out] input_buf Pointer to input buffer
+ * @param[in] blockSize block Size
+ * @param[in] guard_bits guard bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param[in] num_adds number of additions
+ * @return guard bits
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Apply guard bits to buffer
+ * @param[in,out] pIn pointer to input buffer
+ * @param[in] numSamples number of samples in the input buffer
+ * @param[in] guard_bits guard bits
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t *pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param[in] numShifts number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param[in] pIn pointer to input buffer
+ * @param[out] pOut pointer to output buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t *pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param[in,out] pIn input buffer
+ * @param[in] numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if (pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if ( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h new file mode 100644 index 0000000..5a18734 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h @@ -0,0 +1,63 @@ +/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+#endif
+
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