From 86608c6770cf08c138a2bdab5855072f64be09ef Mon Sep 17 00:00:00 2001 From: joshua Date: Sat, 30 Dec 2023 23:54:31 -0500 Subject: initial commit --- .../Examples/ARM/arm_variance_example/Abstract.txt | 4 + .../ARM/arm_variance_example/CMakeLists.txt | 46 +++++ .../RTE/Device/ARMCM0/startup_ARMCM0.s | 159 +++++++++++++++ .../RTE/Device/ARMCM0/system_ARMCM0.c | 56 +++++ .../RTE/Device/ARMCM3/startup_ARMCM3.s | 163 +++++++++++++++ .../RTE/Device/ARMCM3/system_ARMCM3.c | 68 +++++++ .../RTE/Device/ARMCM4_FP/startup_ARMCM4.s | 163 +++++++++++++++ .../RTE/Device/ARMCM4_FP/system_ARMCM4.c | 83 ++++++++ .../RTE/Device/ARMCM7_SP/startup_ARMCM7.s | 163 +++++++++++++++ .../RTE/Device/ARMCM7_SP/system_ARMCM7.c | 85 ++++++++ .../arm_variance_example_f32.c | 225 +++++++++++++++++++++ 11 files changed, 1215 insertions(+) create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c create mode 100644 Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c (limited to 'Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example') diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt new file mode 100644 index 0000000..4dc03b8 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_variance_example for + Cortex-M0, Cortex-M3, Cortex-M4 with FPU and Cortex-M7 with single precision FPU. + +The example is configured for uVision Simulator. diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt new file mode 100644 index 0000000..60f2341 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/CMakeLists.txt @@ -0,0 +1,46 @@ +cmake_minimum_required (VERSION 3.6) +project (arm_variance_example VERSION 0.1) + +# Needed to include the configBoot module +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../../..) + +################################### +# +# LIBRARIES +# +################################### + +########### +# +# CMSIS DSP +# + +add_subdirectory(../../../Source bin_dsp) + + +################################### +# +# TEST APPLICATION +# +################################### + + +add_executable(arm_variance_example) + +set(ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../../../../..) + +include(configBoot) + +target_sources(arm_variance_example PRIVATE arm_variance_example_f32.c) + +### Sources and libs + +target_link_libraries(arm_variance_example PRIVATE CMSISDSP) + +################################### +# +# INSTALLATION +# +################################### + +install (TARGETS arm_variance_example DESTINATION "${PROJECT_SOURCE_DIR}/varianceExampleBuild.axf") \ No newline at end of file diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..bdb4be7 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,159 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE ( 22 * 4) ; Interrupts 10 .. 31 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..d735adf --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..81a33d9 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..5578e23 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..93f7f27 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..cfac6b2 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..f9d954a --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,163 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..affc835 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c new file mode 100644 index 0000000..b980309 --- /dev/null +++ b/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2012 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.0 +* +* Project: CMSIS DSP Library +* Title: arm_variance_example_f32.c +* +* Description: Example code demonstrating variance calculation of input sequence. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup VarianceExample Variance Example + * + * \par Description: + * \par + * Demonstrates the use of Basic Math and Support Functions to calculate the variance of an + * input sequence with N samples. Uniformly distributed white noise is taken as input. + * + * \par Algorithm: + * \par + * The variance of a sequence is the mean of the squared deviation of the sequence from its mean. + * \par + * This is denoted by the following equation: + * 
 variance = ((x[0] - x') * (x[0] - x') + (x[1] - x') * (x[1] - x') + ... + * (x[n-1] - x') * (x[n-1] - x')) / (N-1)
+ * where, x[n] is the input sequence, N is the number of input samples, and + * x' is the mean value of the input sequence, x[n]. + * \par + * The mean value x' is defined as: + * 
 x' = (x[0] + x[1] + ... + x[n-1]) / N
+ * + * \par Block Diagram: + * \par + * \image html Variance.gif + * + * + * \par Variables Description: + * \par + * \li \c testInput_f32 points to the input data + * \li \c wire1, \c wir2, \c wire3 temporary buffers + * \li \c blockSize number of samples processed at a time + * \li \c refVarianceOut reference variance value + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_dot_prod_f32() + * - arm_mult_f32() + * - arm_sub_f32() + * - arm_fill_f32() + * - arm_copy_f32() + * + * Refer + * \link arm_variance_example_f32.c \endlink + * + */ + + +/** \example arm_variance_example_f32.c + */ + +#include +#include "arm_math.h" + +/* ---------------------------------------------------------------------- +* Defines each of the tests performed +* ------------------------------------------------------------------- */ +#define MAX_BLOCKSIZE 32 +#define DELTA (0.000001f) + + +/* ---------------------------------------------------------------------- +* Declare I/O buffers +* ------------------------------------------------------------------- */ +float32_t wire1[MAX_BLOCKSIZE]; +float32_t wire2[MAX_BLOCKSIZE]; +float32_t wire3[MAX_BLOCKSIZE]; + +/* ---------------------------------------------------------------------- +* Test input data for Floating point Variance example for 32-blockSize +* Generated by the MATLAB randn() function +* ------------------------------------------------------------------- */ + +float32_t testInput_f32[32] = +{ + -0.432564811528221, -1.665584378238097, 0.125332306474831, 0.287676420358549, + -1.146471350681464, 1.190915465642999, 1.189164201652103, -0.037633276593318, + 0.327292361408654, 0.174639142820925, -0.186708577681439, 0.725790548293303, + -0.588316543014189, 2.183185818197101, -0.136395883086596, 0.113931313520810, + 1.066768211359189, 0.059281460523605, -0.095648405483669, -0.832349463650022, + 0.294410816392640, -1.336181857937804, 0.714324551818952, 1.623562064446271, + -0.691775701702287, 0.857996672828263, 1.254001421602532, -1.593729576447477, + -1.440964431901020, 0.571147623658178, -0.399885577715363, 0.689997375464345 + +}; + +/* ---------------------------------------------------------------------- +* Declare Global variables +* ------------------------------------------------------------------- */ +uint32_t blockSize = 32; +float32_t refVarianceOut = 0.903941793931839; + +/* ---------------------------------------------------------------------- +* Variance calculation test +* ------------------------------------------------------------------- */ + +int32_t main(void) +{ + arm_status status; + float32_t mean, oneByBlockSize; + float32_t variance; + float32_t diff; + + status = ARM_MATH_SUCCESS; + +#if defined(FILEIO) + printf("START\n"); +#endif + + + /* Calculation of mean value of input */ + + /* x' = 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + + /* Fill wire1 buffer with 1.0 value */ + arm_fill_f32(1.0, wire1, blockSize); + + /* Calculate the dot product of wire1 and wire2 */ + /* (x(0)* 1 + x(1) * 1 + ...+ x(n-1) * 1) */ + arm_dot_prod_f32(testInput_f32, wire1, blockSize, &mean); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize); + + /* 1/blockSize * (x(0)* 1 + x(1) * 1 + ... + x(n-1) * 1) */ + arm_mult_f32(&mean, &oneByBlockSize, &mean, 1); + + + /* Calculation of variance value of input */ + + /* (1/blockSize) * (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + + /* Fill wire2 with mean value x' */ + arm_fill_f32(mean, wire2, blockSize); + + /* wire3 contains (x-x') */ + arm_sub_f32(testInput_f32, wire2, wire3, blockSize); + + /* wire2 contains (x-x') */ + arm_copy_f32(wire3, wire2, blockSize); + + /* (x(0) - x') * (x(0) - x') + (x(1) - x') * (x(1) - x') + ... + (x(n-1) - x') * (x(n-1) - x') */ + arm_dot_prod_f32(wire2, wire3, blockSize, &variance); + + /* Calculation of 1/blockSize */ + oneByBlockSize = 1.0 / (blockSize - 1); + + /* Calculation of variance */ + arm_mult_f32(&variance, &oneByBlockSize, &variance, 1); + + /* absolute value of difference between ref and test */ + diff = fabsf(refVarianceOut - variance); + + /* Comparison of variance value with reference */ + + if (diff > DELTA) + { + status = ARM_MATH_TEST_FAILURE; + } + + +#if !defined(FILEIO) + if ( status != ARM_MATH_SUCCESS) + { + while (1); + } + + while (1); /* main function does not return */ +#else + if (status == ARM_MATH_SUCCESS) + { + printf("SUCCESS\n"); + } + else + { + printf("FAILURE\n"); + } +#endif +} + + /** \endlink */ + + -- cgit v1.2.3