path: root/verilog/fpu/fpu.v

module fpu
(
	input wire [31:0] fpu_in_1,
	input wire [31:0] fpu_in_2,
	output wire[31:0] fpu_output
);

reg[31:0] tmp_out;
reg[22:0] fpu_reg_1;
reg[22:0] fpu_reg_2;
reg[7:0] exp;

wire [7:0] dif_exp = fpu_in_1[30:23] - fpu_in_2[30:23];
wire [7:0] neg_dif_exp = fpu_in_2[30:23] - fpu_in_1[30:23];

reg[23:0] mantis_sum;

always @ ( * )
begin
	/* $display("\nNEW TEST\n"); */
	/* $display("\nMantissas R1: %16b R2: %16b", fpu_in_1[22:0], fpu_in_2[22:0]); */
	/* $display("\ndif_exp[7]: %16b", dif_exp); */
	if (dif_exp[7] == 1'b1) begin
		fpu_reg_1 = fpu_in_1[22:0] >> 1;
		fpu_reg_1[22] = 1'b1;
		fpu_reg_1 = fpu_reg_1 >> neg_dif_exp-1;
		fpu_reg_2 = fpu_in_2[22:0];
		exp = fpu_in_2[30:23];
		/* $display("\n1 1 smaller exp: %16b", neg_dif_exp, fpu_reg_1[22:0]); */
	end else begin
		if (dif_exp > 8'b0) begin
			fpu_reg_2 = fpu_in_2 >> 1;
			fpu_reg_2[22] = 1'b1;
			fpu_reg_2 = fpu_reg_2 >> dif_exp-1;
			/* $display("\n 2 smaller exp: %16b, shifted R2: %16b", dif_exp, fpu_reg_2[22:0]); */
		end else begin
			fpu_reg_2 = fpu_in_2[22:0];
			/* $display("\nexp equal"); */
		end
		fpu_reg_1 = fpu_in_1[22:0];
		exp = fpu_in_1[30:23];
	end

	/* $display("\nDenormalized mantissas: 1: %16b, 2: %16b: ", fpu_reg_1, fpu_reg_2); */
	/* $display("\nexp: %16b", exp); */

	mantis_sum = fpu_reg_1 + fpu_reg_2;

	/* $display("\nmantis: %16b, exp:%16b", mantis_sum, exp); */

	if (mantis_sum[23] == 1'b1) begin
		exp = exp + 1;
		mantis_sum = mantis_sum >> 1'b1;
		if (dif_exp == 8'b0) begin
			mantis_sum[22] = 1'b1;
		end else begin
			mantis_sum[22] = 1'b0;
		end

		/* $display("\nshifted exp: %16b", exp); */
		/* $display("\nshifted mantis: %16b", mantis_sum); */
	end


	tmp_out[31] = 1'b0;
	tmp_out[30:23] = exp;
	tmp_out[22:0] = mantis_sum[22:0];
end

assign fpu_output = tmp_out;
endmodule