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author | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
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committer | joshua <joshua@joshuayun.com> | 2022-04-16 23:00:55 -0500 |
commit | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (patch) | |
tree | c337d4454d3a4d5aa01ad3531e8c723b09fe7d0e /verilog/alu/alu.v | |
parent | 2f1be3c7aabb42ac3ad4347595d5d7be0e2ad6a0 (diff) | |
download | riscv-processor-inorder-d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c.tar.gz |
Added pdfs and more alu stuff
Diffstat (limited to 'verilog/alu/alu.v')
-rw-r--r-- | verilog/alu/alu.v | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/verilog/alu/alu.v b/verilog/alu/alu.v new file mode 100644 index 0000000..3a4213a --- /dev/null +++ b/verilog/alu/alu.v @@ -0,0 +1,26 @@ +`include "aluOp.vh" + +module riscv_alu +( +input wire [31:0] alu_in_1, +input wire[31:0] alu_in_2, +input wire[3:0] alu_op_i, +output wire[31:0] alu_output +); + + +wire diff = alu_in_1 - alu_in_2; +wire ones = 32'hFFFFFFFF; + +assign alu_output = alu_op_i == ADD ? alu_in_1 + alu_in_2 : + alu_op_i == SUB ? diff : + alu_op_i == XOR ? alu_in_1 ^ alu_in_2 : + alu_op_i == OR ? alu_in_1 | alu_in_2 : + alu_op_i == AND ? alu_in_1 & alu_in_2 : + alu_op_i == SLL ? alu_in_1 << alu_in_2 : + alu_op_i == SRL ? alu_in_1 >> alu_in_2 : + alu_op_i == SLT ? (alu_in_1 < alu_in_2 ? 32'b1 : 32'b0) : + alu_op_i == NONE ? alu_in_1 : 32'b0 : + alu_op_i == SLTU ? (alu_in_1[31] == alu_in_2[31] ? (diff[31] == 0 ? 0 : 1) : (alu_in_1[31] == 1 ? 1 : 0) ) : + alu_op_i == SRA ? alu_in_1[31] == 0 ? alu_in_1 >> alu_in_2 : ; +endmodule |