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| author | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
|---|---|---|
| committer | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
| commit | c1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch) | |
| tree | bd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v1/Makefile | |
| parent | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff) | |
| download | riscv-processor-inorder-master.tar.gz | |
Diffstat (limited to 'verilog/alu/v1/Makefile')
| -rw-r--r-- | verilog/alu/v1/Makefile | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/verilog/alu/v1/Makefile b/verilog/alu/v1/Makefile deleted file mode 100644 index 74816c7..0000000 --- a/verilog/alu/v1/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -PROJ=alu -VERION:=r0.2 -RM = rm -rf -COPY = cp -a -PATH_SEP = / - - -crab: ${PROJ}.dfu - -dfu: ${PROJ}.dfu - dfu-util -D $< - - -%.json: %.v - yosys -p "read_verilog $<; synth_ecp5 -top ${PROJ} -json $@" - -%_out.config: %.json - nextpnr-ecp5 --json $< --textcfg $@ --25k --package CSFBGA285 --lpf crab.pcf - -%.bit: %_out.config - ecppack --compress --freq 38.8 --input $< --bit $@ - -%.dfu : %.bit - $(COPY) $< $@ - dfu-suffix -v 1209 -p 5af0 -a $@ - -sim: - verilator -Wall --cc --exe --build tbalu.cpp alu.v --trace && ./obj_dir/Valu > out -simclean: - rm -rf obj_dir/* out - -clean: - $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu - -.PHONY: prog clean |