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authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v1/tbalu.cpp
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-master.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/alu/v1/tbalu.cpp')
-rw-r--r--verilog/alu/v1/tbalu.cpp45
1 files changed, 0 insertions, 45 deletions
diff --git a/verilog/alu/v1/tbalu.cpp b/verilog/alu/v1/tbalu.cpp
deleted file mode 100644
index b3947f8..0000000
--- a/verilog/alu/v1/tbalu.cpp
+++ /dev/null
@@ -1,45 +0,0 @@
-#include <stdlib.h>
-#include <iostream>
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-#include "Valu.h"
-#include "aluOp.h"
-#define OP SRA
-#define OPSTR "SRA"
-#define SIGN "SRA"
-#define LOWER -10
-#define UPPER 0
-
-vluint64_t sim_time = 0;
-
-int main(int argc, char** argv, char** env) {
- Valu *dut = new Valu;
-
- Verilated::traceEverOn(true);
- VerilatedVcdC *m_trace = new VerilatedVcdC;
- dut->trace(m_trace, 5);
- m_trace->open("waveform.vcd");
-
- dut->op = OP;
- for (dut->in1 = LOWER; (int) dut->in1 < UPPER; dut->in1++) {
- for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) {
- dut->eval();
- std::cout << OPSTR << ": " << (int) dut->in1 << " " << SIGN << " " << (int) dut->in2 << " = " << (int) dut->out << "\n";
- sim_time++;
- m_trace->dump(sim_time);
- }
- }
-
- for (dut->in1 = 1; (int) dut->in1 < 10; dut->in1++) {
- for (dut->in2 = 0; (int) dut->in2 < 10; dut->in2++) {
- dut->eval();
- std::cout << OPSTR << ": " << dut->in1 << " " << SIGN << " " << dut->in2 << " = " << dut->out << "\n";
- sim_time++;
- m_trace->dump(sim_time);
- }
- }
-
- m_trace->close();
- delete dut;
- exit(EXIT_SUCCESS);
-}