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| author | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
|---|---|---|
| committer | Joshua Yun <jjyun4@illinois.edu> | 2023-08-28 14:42:23 -0500 |
| commit | c1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch) | |
| tree | bd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v3/aluOp.h | |
| parent | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff) | |
| download | riscv-processor-inorder-master.tar.gz | |
Diffstat (limited to 'verilog/alu/v3/aluOp.h')
| -rw-r--r-- | verilog/alu/v3/aluOp.h | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/verilog/alu/v3/aluOp.h b/verilog/alu/v3/aluOp.h deleted file mode 100644 index 999dac2..0000000 --- a/verilog/alu/v3/aluOp.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef ALU_OP -#define ALU_OP - -#define ADD 0 -#define SUB 8 -#define XOR 4 -#define OR 6 -#define AND 7 -#define SLL 1 -#define SRL 5 -#define SRA 13 -#define SLT 2 -#define SLTU 3 -#define NONE 15 - -#endif |