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authorjoshua <joshua@joshuayun.com>2022-05-16 11:05:49 -0400
committerjoshua <joshua@joshuayun.com>2022-05-16 11:05:49 -0400
commitd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (patch)
tree96bc2fd0552a0736b562dc01642cd22d2e7cb7b4 /verilog/alu/v4/Makefile
parent112415c3d50f900f3ee10edd1161eb80b97c42c7 (diff)
downloadriscv-processor-inorder-d069ea63cce08c0f5c8d7da7f8ab05115bd8d856.tar.gz
Fixed gitignore
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