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authorJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
committerJoshua Yun <jjyun4@illinois.edu>2023-08-28 14:42:23 -0500
commitc1fa3c36da28e9e947f6279329c47777f31fe7a2 (patch)
treebd321c8e33200427b23bffe96c7c1bae90d8a044 /verilog/alu/v5/aluOp.vh
parentd069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (diff)
downloadriscv-processor-inorder-master.tar.gz
Added new riscv processor design into git repoHEADmaster
Diffstat (limited to 'verilog/alu/v5/aluOp.vh')
-rw-r--r--verilog/alu/v5/aluOp.vh16
1 files changed, 0 insertions, 16 deletions
diff --git a/verilog/alu/v5/aluOp.vh b/verilog/alu/v5/aluOp.vh
deleted file mode 100644
index b6e916f..0000000
--- a/verilog/alu/v5/aluOp.vh
+++ /dev/null
@@ -1,16 +0,0 @@
-`ifndef ALU_OP
-`define ALU_OP
-
-`define ADD 4'b0000
-`define SUB 4'b1000
-`define XOR 4'b0100
-`define OR 4'b0110
-`define AND 4'b0111
-`define SLL 4'b0001
-`define SRL 4'b0101
-`define SRA 4'b1101
-`define SLT 4'b0010
-`define SLTU 4'b0011
-`define NONE 4'b1111
-
-`endif