Added new riscv processor design into git repoHEADmaster

1 files changed, 0 insertions, 44 deletions

diff --git a/verilog/alu/v6/tbalu.cpp b/verilog/alu/v6/tbalu.cpp
deleted file mode 100644
index 6d02bf3..0000000
--- a/verilog/alu/v6/tbalu.cpp
+++ /dev/null
@@ -1,44 +0,0 @@
-#include <stdlib.h>
-#include <iostream>
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-#include "Valu6.h"
-#include "aluOp.h"
-
-vluint64_t sim_time = 0;
-
-
-void benchmark(Valu6 * dut, VerilatedVcdC *m_trace, int opcodes, char op[6], char sign[6]) {
-
-	dut->alu_op_i = opcodes;
-	for (int i = 0; i < 20; i++) {
-		for (int j = 0; j < 20; j++) {
-			int in1 = i - 10;
-			int in2 = j - 10;
-			dut->alu_in_1 = in1;
-			dut->alu_in_2 = in2;
-			dut->eval();
-			std::cout << op <<(int) (dut->alu_in_1)<< sign << (int) dut->alu_in_2  << " = " << (int) dut->alu_output << "\n";
-			sim_time++;
-			m_trace->dump(sim_time);
-		}
-	}
-}
-
-int main(int argc, char** argv, char** env) {
-	Valu6 *dut = new Valu6;
-	
-	Verilated::traceEverOn(true);
-	VerilatedVcdC *m_trace = new VerilatedVcdC;
-	dut->trace(m_trace, 5);
-	m_trace->open("waveform.vcd");
-	int opcodes[10] = { ADD, SUB, XOR, OR, AND, SLL, SRL, SRA, SLT, SLTU };
-	char ops[10][6] = { "ADD: ", "SUB: ", "XOR: ", "OR: ", "AND: ", "SLL: ", "SRL: ", "SRA: ", "SLT: ", "SLTU:" };
-	char signs[10][6] = { " + ", " - ", " ^ ", " | ", " & ", " << ", " >> ", " >>A ", " ? ", " ?U " };
-	//for (int i = 0; i < 10; i++)
-	benchmark(dut, m_trace, SRA, ops[7], signs[7]);
-	
-	m_trace->close();
-	delete dut;
-	exit(EXIT_SUCCESS);
-}