Added pdfs and more alu stuff

2 files changed, 88 insertions, 0 deletions

diff --git a/verilog/register/a.out b/verilog/register/a.out
new file mode 100755
index 0000000..f6d832d
--- /dev/null
+++ b/verilog/register/a.out
@@ -0,0 +1,66 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)" "(v11_0)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/ivl/system.vpi";
+:vpi_module "/usr/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/ivl/va_math.vpi";
+S_0x55bafda5d0c0 .scope module, "registers" "registers" 2 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "writeEnable";
+    .port_info 1 /INPUT 1 "clk";
+    .port_info 2 /INPUT 32 "addr1";
+    .port_info 3 /INPUT 32 "addr2";
+    .port_info 4 /INPUT 32 "addr3";
+    .port_info 5 /INPUT 32 "writeData";
+    .port_info 6 /OUTPUT 32 "readData1";
+    .port_info 7 /OUTPUT 32 "readData2";
+L_0x55bafda6fe60 .functor BUFZ 32, L_0x55bafda6fda0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0x55bafda6ffa0 .functor BUFZ 32, L_0x55bafda6fed0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+v0x55bafda5d340_0 .net *"_ivl_0", 31 0, L_0x55bafda6fda0;  1 drivers
+v0x55bafda6f380_0 .net *"_ivl_4", 31 0, L_0x55bafda6fed0;  1 drivers
+o0x7fee24862078 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55bafda6f460_0 .net "addr1", 31 0, o0x7fee24862078;  0 drivers
+o0x7fee248620a8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55bafda6f520_0 .net "addr2", 31 0, o0x7fee248620a8;  0 drivers
+o0x7fee248620d8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55bafda6f600_0 .net "addr3", 31 0, o0x7fee248620d8;  0 drivers
+o0x7fee24862108 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55bafda6f730_0 .net "clk", 0 0, o0x7fee24862108;  0 drivers
+v0x55bafda6f7f0_0 .net "readData1", 31 0, L_0x55bafda6fe60;  1 drivers
+v0x55bafda6f8d0_0 .net "readData2", 31 0, L_0x55bafda6ffa0;  1 drivers
+v0x55bafda6f9b0 .array "register", 31 0, 31 0;
+o0x7fee24862198 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0x55bafda6fb00_0 .net "writeData", 31 0, o0x7fee24862198;  0 drivers
+o0x7fee248621c8 .functor BUFZ 1, C4<z>; HiZ drive
+v0x55bafda6fbe0_0 .net "writeEnable", 0 0, o0x7fee248621c8;  0 drivers
+E_0x55bafda5d640 .event posedge, v0x55bafda6f730_0;
+L_0x55bafda6fda0 .array/port v0x55bafda6f9b0, o0x7fee24862078;
+L_0x55bafda6fed0 .array/port v0x55bafda6f9b0, o0x7fee248620a8;
+    .scope S_0x55bafda5d0c0;
+T_0 ;
+    %wait E_0x55bafda5d640;
+    %load/vec4 v0x55bafda6fbe0_0;
+    %flag_set/vec4 8;
+    %jmp/0 T_0.0, 8;
+    %load/vec4 v0x55bafda6fb00_0;
+    %jmp/1 T_0.1, 8;
+T_0.0 ; End of true expr.
+    %ix/getv 4, v0x55bafda6f600_0;
+    %load/vec4a v0x55bafda6f9b0, 4;
+    %jmp/0 T_0.1, 8;
+ ; End of false expr.
+    %blend;
+T_0.1;
+    %ix/getv 3, v0x55bafda6f600_0;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0x55bafda6f9b0, 0, 4;
+    %jmp T_0;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "registers.v";
diff --git a/verilog/register/registers.v b/verilog/register/registers.v
new file mode 100644
index 0000000..f2dbb22
--- /dev/null
+++ b/verilog/register/registers.v
@@ -0,0 +1,22 @@
+module registers(
+	input wire writeEnable,
+	input wire clk,
+	input wire [31:0] addr1,
+	input wire [31:0] addr2,
+	input wire [31:0] addr3,
+	input wire [31:0] writeData,
+	output wire [31:0] readData1,
+	output wire [31:0] readData2
+);
+
+reg [31:0] register [0:31];
+
+always @ (posedge clk)
+begin
+	register[addr3] <= writeEnable ? writeData : register[addr3];
+end
+
+assign readData1 = register[addr1];
+assign readData2 = register[addr2];
+
+endmodule