Added pdfs and more alu stuff

1 files changed, 0 insertions, 39 deletions

diff --git a/verilog/riscv_alu.v b/verilog/riscv_alu.v
deleted file mode 100644
index 87dd637..0000000
--- a/verilog/riscv_alu.v
+++ /dev/null
@@ -1,39 +0,0 @@
-module riscv_alu
-(
-input wire signed [31:0] alu_in_1,
-input wire[31:0] alu_in_2,
-input wire[3:0] alu_op_i,
-output wire[31:0] alu_output
-);
-
-reg[31:0] tmp_out;
-`include "alu_ops.vh"
-
-wire [31:0] sub_alu = alu_in_1 - alu_in_2;
-
-always @(*)
-begin
-	case (alu_op_i)
-		`ADD: tmp_out = alu_in_1 + alu_in_2;
-		`SUB: tmp_out = sub_alu;
-		`XOR: tmp_out = alu_in_1 ^ alu_in_2;
-		`OR: tmp_out = alu_in_1 | alu_in_2;
-		`AND: tmp_out = alu_in_1 & alu_in_2;
-		`SLL: tmp_out = alu_in_1 << alu_in_2;
-		`SRL: tmp_out = alu_in_1 >> alu_in_2;
-		`SRA: tmp_out = alu_in_1 >>> alu_in_2;
-		`SLT: tmp_out = (alu_in_1 < alu_in_2) ? 32'h1 : 32'h0;
-		`SLTU:
-		begin
-			if (alu_in_1[31] != alu_in_2[31])
-			    tmp_out  = alu_in_1[31] ? 32'h1 : 32'h0;
-			else
-			    tmp_out = sub_alu[31] ? 32'h1 : 32'h0;
-		end
-		default: tmp_out = alu_in_1;
-	endcase
-end
-
-assign alu_output = tmp_out;
-
-endmodule