diff options
Diffstat (limited to 'verilog/alu/tbalu.v')
| -rw-r--r-- | verilog/alu/tbalu.v | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/verilog/alu/tbalu.v b/verilog/alu/tbalu.v new file mode 100644 index 0000000..7ffc8bf --- /dev/null +++ b/verilog/alu/tbalu.v @@ -0,0 +1,50 @@ +`timescale 1us/1ns + +`include "alu_ops.vh" +`include "alu.v" + +module tbalu; + +reg [31:0] in1,in2; +wire [31:0] out; +reg [3:0] op; + +alu alu0 (in1, in2,op, out); + +initial begin + in1=-32'b1; + in2=32'b1; + op=`ADD; + #5 + $display("\nPlus:\t\t %d %32b + %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SUB; + #5 + $display("\nMinus:\t\t %d %32b - %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`XOR; + #5 + $display("\nXor:\t\t %d %32b ^ %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`OR; + #5 + $display("\nOr:\t\t %d %32b | %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`AND; + #5 + $display("\nAnd:\t\t %d %32b & %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SLL; + #5 + $display("\nLeft Logical:\t %d %32b << %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SRL; + #5 + $display("\nRight Logical:\t %d %32b >> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SRA; + #5 + $display("\nRight Arith:\t %d %32b >>> %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SLT; + #5 + $display("\nSet Less:\t %d %32b < %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + op=`SLTU; + #5 + $display("\nSet Less U:\t %d %32b < U %d %32b = %d %32b", $signed(in1), in1, $signed(in2), in2, $signed(out), out); + $finish; +end + +endmodule |