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Diffstat (limited to 'verilog/alu/v6/Makefile')
| -rw-r--r-- | verilog/alu/v6/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/verilog/alu/v6/Makefile b/verilog/alu/v6/Makefile index 437e09f..02598ac 100644 --- a/verilog/alu/v6/Makefile +++ b/verilog/alu/v6/Makefile @@ -32,7 +32,7 @@ simgate: verilator -Wall --cc --exe --build tbalu.cpp synth_alu6.v --trace && ./obj_dir/Valu6 > out simclean: - rm -rf obj_dir/* out + rm -rf obj_dir/* out waveform.vcd clean: $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu |