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| author | joshua <joshua@joshuayun.com> | 2022-05-16 11:05:49 -0400 |
|---|---|---|
| committer | joshua <joshua@joshuayun.com> | 2022-05-16 11:05:49 -0400 |
| commit | d069ea63cce08c0f5c8d7da7f8ab05115bd8d856 (patch) | |
| tree | 96bc2fd0552a0736b562dc01642cd22d2e7cb7b4 /verilog/alu/v6/Makefile | |
| parent | 112415c3d50f900f3ee10edd1161eb80b97c42c7 (diff) | |
| download | riscv-processor-inorder-d069ea63cce08c0f5c8d7da7f8ab05115bd8d856.tar.gz | |
Fixed gitignore
Diffstat (limited to 'verilog/alu/v6/Makefile')
| -rw-r--r-- | verilog/alu/v6/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/verilog/alu/v6/Makefile b/verilog/alu/v6/Makefile index 437e09f..02598ac 100644 --- a/verilog/alu/v6/Makefile +++ b/verilog/alu/v6/Makefile @@ -32,7 +32,7 @@ simgate: verilator -Wall --cc --exe --build tbalu.cpp synth_alu6.v --trace && ./obj_dir/Valu6 > out simclean: - rm -rf obj_dir/* out + rm -rf obj_dir/* out waveform.vcd clean: $(RM) -f ${PROJ}.bit ${PROJ}_out.config ${PROJ}.json ${PROJ}.dfu |