diff options
Diffstat (limited to 'verilog/alu/v6/alu6.blif')
| -rw-r--r-- | verilog/alu/v6/alu6.blif | 6128 |
1 files changed, 6128 insertions, 0 deletions
diff --git a/verilog/alu/v6/alu6.blif b/verilog/alu/v6/alu6.blif new file mode 100644 index 0000000..33840f9 --- /dev/null +++ b/verilog/alu/v6/alu6.blif @@ -0,0 +1,6128 @@ +# Generated by Yosys 0.15+70 (git sha1 48d7a6c47, gcc 11.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os) + +.model alu6 +.inputs alu_in_1[0] alu_in_1[1] alu_in_1[2] alu_in_1[3] alu_in_1[4] alu_in_1[5] alu_in_1[6] alu_in_1[7] alu_in_1[8] alu_in_1[9] alu_in_1[10] alu_in_1[11] alu_in_1[12] alu_in_1[13] alu_in_1[14] alu_in_1[15] alu_in_1[16] alu_in_1[17] alu_in_1[18] alu_in_1[19] alu_in_1[20] alu_in_1[21] alu_in_1[22] alu_in_1[23] alu_in_1[24] alu_in_1[25] alu_in_1[26] alu_in_1[27] alu_in_1[28] alu_in_1[29] alu_in_1[30] alu_in_1[31] alu_in_2[0] alu_in_2[1] alu_in_2[2] alu_in_2[3] alu_in_2[4] alu_in_2[5] alu_in_2[6] alu_in_2[7] alu_in_2[8] alu_in_2[9] alu_in_2[10] alu_in_2[11] alu_in_2[12] alu_in_2[13] alu_in_2[14] alu_in_2[15] alu_in_2[16] alu_in_2[17] alu_in_2[18] alu_in_2[19] alu_in_2[20] alu_in_2[21] alu_in_2[22] alu_in_2[23] alu_in_2[24] alu_in_2[25] alu_in_2[26] alu_in_2[27] alu_in_2[28] alu_in_2[29] alu_in_2[30] alu_in_2[31] alu_op_i[0] alu_op_i[1] alu_op_i[2] alu_op_i[3] +.outputs alu_output[0] alu_output[1] alu_output[2] alu_output[3] alu_output[4] alu_output[5] alu_output[6] alu_output[7] alu_output[8] alu_output[9] alu_output[10] alu_output[11] alu_output[12] alu_output[13] alu_output[14] alu_output[15] alu_output[16] alu_output[17] alu_output[18] alu_output[19] alu_output[20] alu_output[21] alu_output[22] alu_output[23] alu_output[24] alu_output[25] alu_output[26] alu_output[27] alu_output[28] alu_output[29] alu_output[30] alu_output[31] +.names $false +.names $true +1 +.names $undef +.gate L6MUX21 D0=alu_output_L6MUX21_Z_D0 D1=alu_output_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] Z=alu_output[24] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_L6MUX21_Z_1_D0 D1=alu_output_L6MUX21_Z_1_D1 SD=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] Z=alu_output[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] Z=alu_output_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] Z=alu_output_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] Z=alu_output_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000001000000 +.gate L6MUX21 D0=alu_output_L6MUX21_Z_2_D0 D1=alu_output_L6MUX21_Z_2_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0 D1=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] Z=alu_output_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0 D1=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] Z=alu_output_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] Z=alu_output_L6MUX21_Z_2_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0100111101000100 +.gate L6MUX21 D0=alu_output_L6MUX21_Z_3_D0 D1=alu_output_L6MUX21_Z_3_D1 SD=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] Z=alu_output[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] Z=alu_output_L6MUX21_Z_3_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_3_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] Z=alu_output_L6MUX21_Z_3_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] Z=alu_output_L6MUX21_Z_3_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000001000000 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] Z=alu_output_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111110 +.gate LUT4 A=alu_output_LUT4_Z_A[0] B=alu_output_LUT4_Z_A[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] D=alu_output_LUT4_Z_A[3] Z=alu_output[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101111111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_1_B[1] D=alu_output_LUT4_Z_1_B[2] Z=alu_output[28] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B[0] C=alu_output_LUT4_Z_10_B[1] D=alu_output_LUT4_Z_10_B[2] Z=alu_output[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[8] C=alu_output_LUT4_Z_10_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_10_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_10_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[16] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[16] D=alu_in_2[16] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[16] D=alu_in_2[16] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000010111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] C=alu_op_i[3] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[24] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[24] D=alu_in_2[24] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[24] D=alu_in_2[24] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT C0=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111001110101010 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z SD=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 SD=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000111111001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000111111001111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_in_2[5] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1010111111001111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=alu_in_1[0] B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000010 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=alu_in_1[0] B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111111111100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111111111100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111011111111 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111011111111 +.gate LUT4 A=$false B=alu_in_1[1] C=alu_in_1[2] D=alu_in_2[0] Z=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_10_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010000000000 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111001111110101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_10_B_LUT4_Z_2_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[8] D=alu_in_2[8] Z=alu_output_LUT4_Z_10_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[8] D=alu_in_2[8] Z=alu_output_LUT4_Z_10_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] C=alu_output_LUT4_Z_11_C[2] D=alu_output_LUT4_Z_11_C[3] Z=alu_output[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111001011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[5] C=alu_output_LUT4_Z_11_C_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_LUT4_Z_C[3] Z=alu_output_LUT4_Z_11_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_11_C_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[5] D=alu_in_2[5] Z=alu_output_LUT4_Z_11_C_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_11_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100111101000100 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[0] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[9] D=alu_in_2[9] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000011111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[9] D=alu_in_2[9] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_1_Z C0=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[17] D=alu_in_2[17] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_in_1[17] B=alu_in_2[17] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[17] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[1] D=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[1] D=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_in_1[3] C=alu_in_1[4] D=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_1[1] C=alu_in_1[2] D=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101111100111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101000001100 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] B=alu_in_2[2] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111101011111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_11_C_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] C=alu_output_LUT4_Z_12_C[2] D=alu_output_LUT4_Z_12_C[3] Z=alu_output[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111100011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_12_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[4] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[4] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_5_B_LUT4_Z_A[2] D=alu_in_2[5] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000000001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A[0] C=alu_output_LUT4_Z_5_B_LUT4_Z_A[1] D=alu_in_2[5] Z=alu_output_LUT4_Z_12_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000000000011 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[2] C=alu_output_LUT4_Z_12_C_LUT4_Z_C[2] D=alu_output_LUT4_Z_12_C_LUT4_Z_C[3] Z=alu_output_LUT4_Z_12_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[2] D=alu_in_2[2] Z=alu_output_LUT4_Z_12_C_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[2] D=alu_in_2[2] Z=alu_output_LUT4_Z_12_C_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111000 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_1_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[28] C=alu_output_LUT4_Z_1_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_1_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_1_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] B=alu_in_2[2] C=alu_in_2[3] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0 D1=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_3_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[30] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[31] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[29] Z=alu_output_LUT4_Z_1_B_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[28] D=alu_in_2[28] Z=alu_output_LUT4_Z_1_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[28] D=alu_in_2[28] Z=alu_output_LUT4_Z_1_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_2_A[1] C=alu_output_LUT4_Z_2_A[2] D=alu_output_LUT4_Z_2_A[3] Z=alu_output[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1 SD=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111111110000 +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[25] D=alu_in_2[25] Z=alu_output_LUT4_Z_2_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT C0=sum[25] Z=alu_output_LUT4_Z_2_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_2_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_2_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000001100000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_2_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_in_2[25] B=alu_in_1[25] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] Z=alu_output_LUT4_Z_2_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000001111111 +.gate LUT4 A=$false B=alu_in_2[25] C=alu_in_1[25] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] Z=alu_output_LUT4_Z_2_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0011111111111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[20] C=alu_output_LUT4_Z_3_C[2] D=alu_output_LUT4_Z_3_C[3] Z=alu_output[20] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111100011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_3_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_A[1] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[0] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_in_2[5] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=$false B=alu_in_1[19] C=alu_in_1[20] D=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] Z=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000001111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_3_C_LUT4_Z_C[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_C[3] Z=alu_output_LUT4_Z_3_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000001011 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100111101000100 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[3] C=alu_in_2[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[4] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[4] D=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[4] D=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[0] B=alu_in_2[2] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000001011 +.gate L6MUX21 D0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=alu_in_2[5] D=alu_in_2[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_op_i[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111101011111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101111100111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_3_C_LUT4_Z_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[20] D=alu_in_2[20] Z=alu_output_LUT4_Z_3_C_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[20] D=alu_in_2[20] Z=alu_output_LUT4_Z_3_C_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_4_C[2] D=alu_output_LUT4_Z_4_C[3] Z=alu_output[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_4_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111000011110011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_4_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011110011 +.gate PFUMX ALUT=alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] Z=alu_output_LUT4_Z_4_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_4_C_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] B=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[19] Z=alu_output_LUT4_Z_4_C_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000011101110111 +.gate LUT4 A=$false B=$false C=alu_in_1[19] D=alu_in_2[19] Z=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[19] D=alu_in_2[19] Z=alu_output_LUT4_Z_4_C_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] D=alu_output_LUT4_Z_5_B[2] Z=alu_output[18] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000011111111 +.gate LUT4 A=alu_output_LUT4_Z_5_B_LUT4_Z_A[2] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_5_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_5_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_5_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1011000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] B=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] D=alu_in_2[3] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[7] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_in_1[4] B=alu_in_1[5] C=alu_in_2[0] D=alu_in_2[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate LUT4 A=alu_in_1[2] B=alu_in_1[3] C=alu_in_2[1] D=alu_in_2[0] Z=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] C=alu_in_1[18] D=alu_in_2[18] Z=alu_output_LUT4_Z_5_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] C=alu_in_2[18] D=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] Z=alu_output_LUT4_Z_5_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000111100110011 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[18] Z=alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_5_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_5_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_5_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_output_LUT4_Z_6_A[0] B=alu_output_LUT4_Z_6_A[1] C=alu_output_LUT4_Z_6_A[2] D=alu_output_LUT4_Z_6_A[3] Z=alu_output[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_6_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] D=alu_in_2[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] D=alu_in_2[2] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[29] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[30] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_2[0] C=alu_in_2[1] D=alu_in_1[31] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[15] D=alu_in_2[15] Z=alu_output_LUT4_Z_6_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] B=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_6_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT C0=sum[15] Z=alu_output_LUT4_Z_6_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_in_2[15] B=alu_in_1[15] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] Z=alu_output_LUT4_Z_6_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000001111111 +.gate LUT4 A=$false B=alu_in_2[15] C=alu_in_1[15] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] Z=alu_output_LUT4_Z_6_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0011111111111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A[0] B=alu_output_LUT4_Z_7_A[1] C=alu_output_LUT4_Z_7_A[2] D=alu_output_LUT4_Z_7_A[3] Z=alu_output[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111111011111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[13] D=alu_in_2[13] Z=alu_output_LUT4_Z_7_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_7_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_7_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_op_i[2] Z=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[2] Z=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT C0=sum[13] Z=alu_output_LUT4_Z_7_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_in_2[13] B=alu_in_1[13] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] Z=alu_output_LUT4_Z_7_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000001111111 +.gate LUT4 A=$false B=alu_in_2[13] C=alu_in_1[13] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] Z=alu_output_LUT4_Z_7_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0011111111111111 +.gate LUT4 A=alu_output_LUT4_Z_8_A[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] C=alu_output_LUT4_Z_8_A[2] D=alu_output_LUT4_Z_8_A[3] Z=alu_output[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010011111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[12] C=alu_output_LUT4_Z_8_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_8_A_LUT4_Z_C[3] Z=alu_output_LUT4_Z_8_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] Z=alu_output_LUT4_Z_8_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000011101111 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[1] B=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[2] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100101000000000 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101000001100 +.gate LUT4 A=alu_output_LUT4_Z_1_B_LUT4_Z_1_A[3] B=alu_in_2[2] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[10] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[8] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[9] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=alu_in_2[4] D=alu_in_2[5] Z=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000000000001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_8_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[12] D=alu_in_2[12] Z=alu_output_LUT4_Z_8_A_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[12] D=alu_in_2[12] Z=alu_output_LUT4_Z_8_A_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B[0] C=alu_output_LUT4_Z_9_B[1] D=alu_output_LUT4_Z_9_B[2] Z=alu_output[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_9_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111010111110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[3] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_in_1[5] C=alu_in_1[6] D=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_1[3] C=alu_in_1[4] D=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[3] D=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT C0=alu_in_2[3] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] C=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000111111001100 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000010100000011 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[13] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[11] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[14] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[12] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[15] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[16] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110000000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[11] C=alu_output_LUT4_Z_9_B_LUT4_Z_C[2] D=alu_output_LUT4_Z_9_B_LUT4_Z_C[3] Z=alu_output_LUT4_Z_9_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_LUT4_Z_9_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1010111111001111 +.gate L6MUX21 D0=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_C_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1010111111001111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[11] D=alu_in_2[11] Z=alu_output_LUT4_Z_9_B_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[11] D=alu_in_2[11] Z=alu_output_LUT4_Z_9_B_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1100110000001100 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0011001100000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] B=alu_in_2[5] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_in_1[4] C=alu_in_1[5] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[2] C=alu_in_1[3] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[0] C=alu_in_1[1] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_A_LUT4_Z_A[2] D=alu_output_LUT4_Z_A_LUT4_Z_A[3] Z=alu_output_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000011100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[11] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[10] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000010100000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_in_2[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=alu_op_i[3] D=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011110000 +.gate LUT4 A=$false B=alu_in_2[5] C=alu_in_2[6] D=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] C=alu_op_i[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111110000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[0] C=alu_in_1[0] D=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101110011001111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] C=sum[31] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1100110000001111 +.gate CCU2C A0=alu_in_1[30] A1=alu_in_1[31] B0=alu_in_2[30] B1=alu_in_2[31] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[0] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[30] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[8] A1=alu_in_1[9] B0=alu_in_2[8] B1=alu_in_2[9] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[8] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[6] A1=alu_in_1[7] B0=alu_in_2[6] B1=alu_in_2[7] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[8] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[6] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[16] A1=alu_in_1[17] B0=alu_in_2[16] B1=alu_in_2[17] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[16] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[14] A1=alu_in_1[15] B0=alu_in_2[14] B1=alu_in_2[15] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[16] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[14] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[12] A1=alu_in_1[13] B0=alu_in_2[12] B1=alu_in_2[13] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[14] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[12] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[10] A1=alu_in_1[11] B0=alu_in_2[10] B1=alu_in_2[11] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[10] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[12] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[10] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[0] A1=alu_in_1[1] B0=alu_in_2[0] B1=alu_in_2[1] C0=$true C1=$true CIN=$true COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[0] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[4] A1=alu_in_1[5] B0=alu_in_2[4] B1=alu_in_2[5] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[6] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[4] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[2] A1=alu_in_1[3] B0=alu_in_2[2] B1=alu_in_2[3] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[2] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[4] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[2] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[28] A1=alu_in_1[29] B0=alu_in_2[28] B1=alu_in_2[29] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[30] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[28] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[26] A1=alu_in_1[27] B0=alu_in_2[26] B1=alu_in_2[27] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[28] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[26] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[24] A1=alu_in_1[25] B0=alu_in_2[24] B1=alu_in_2[25] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[26] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[24] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[22] A1=alu_in_1[23] B0=alu_in_2[22] B1=alu_in_2[23] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[24] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[22] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[20] A1=alu_in_1[21] B0=alu_in_2[20] B1=alu_in_2[21] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[22] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[20] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[18] A1=alu_in_1[19] B0=alu_in_2[18] B1=alu_in_2[19] C0=$true C1=$true CIN=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[18] COUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[20] D0=$true D1=$true S0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[18] S1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:27.29-27.48|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate LUT4 A=$false B=$false C=sum[0] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100111101000100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[13] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[12] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[5] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[4] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[7] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[6] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B[1] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111010111110011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[0] C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[21] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000101110111011 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT C0=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[0] C=alu_in_1[21] D=alu_in_2[21] Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0101110011001111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 SD=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[9] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[8] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_LUT4_Z_A_LUT4_Z_1_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=alu_in_1[29] B=alu_in_2[29] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_LUT4_Z_A_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[29] D=alu_in_2[29] Z=alu_output_LUT4_Z_A_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] C=alu_in_2[2] D=alu_in_2[3] Z=alu_output_LUT4_Z_A_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0 D1=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1 SD=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[17] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT BLUT=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=alu_in_1[30] D=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=alu_in_1[29] C=alu_in_1[31] D=alu_in_2[1] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[2] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[29] Z=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0[4] Z=alu_output[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_ALUT BLUT=alu_output_PFUMX_Z_1_BLUT C0=alu_output_PFUMX_Z_1_C0[4] Z=alu_output[30] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_PFUMX_Z_10_ALUT BLUT=alu_output_PFUMX_Z_10_BLUT C0=alu_output_PFUMX_Z_10_C0[4] Z=alu_output[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_10_C0[0] B=alu_output_PFUMX_Z_10_C0[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_PFUMX_Z_10_C0[3] Z=alu_output_PFUMX_Z_10_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111100000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_10_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[10] C=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] D=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_10_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_10_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[1] D=alu_in_2[2] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] D=alu_in_2[2] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_10_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[10] D=alu_in_2[10] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[10] D=alu_in_2[10] Z=alu_output_PFUMX_Z_10_C0_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_10_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_10_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110000000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_10_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_11_ALUT BLUT=alu_output_PFUMX_Z_11_BLUT C0=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[4] Z=alu_output[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[9] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] D=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] Z=alu_output_PFUMX_Z_11_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111111000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_11_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_12_ALUT BLUT=alu_output_PFUMX_Z_12_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] Z=alu_output[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] B=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] C=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] D=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_12_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111010011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_12_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100010100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate PFUMX ALUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT BLUT=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT C0=alu_in_2[3] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] C=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[1] D=alu_in_2[2] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] Z=alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_13_ALUT BLUT=alu_output_PFUMX_Z_13_BLUT C0=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[4] Z=alu_output[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] B=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[3] Z=alu_output_PFUMX_Z_13_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100010000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_13_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_14_ALUT BLUT=alu_output_PFUMX_Z_14_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[4] Z=alu_output[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[3] Z=alu_output_PFUMX_Z_14_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111101000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_14_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0[0] B=alu_output_PFUMX_Z_1_C0[1] C=alu_output_PFUMX_Z_1_C0[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_1_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_1_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] C=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] D=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_1_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000011100000000 +.gate LUT4 A=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] B=alu_in_2[2] C=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_1_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000101100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_in_2[1] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000010100000011 +.gate LUT4 A=$false B=alu_in_1[27] C=alu_in_1[28] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[25] C=alu_in_1[26] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[23] C=alu_in_1[24] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[21] C=alu_in_1[22] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[29] C=alu_in_1[30] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] C=alu_in_2[2] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_PFUMX_Z_1_C0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110000000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] D=alu_in_2[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011001100001111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000000111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_in_2[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111110101111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z BLUT=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate L6MUX21 D0=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z SD=alu_in_2[2] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate LUT4 A=$false B=alu_in_1[17] C=alu_in_1[18] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[15] C=alu_in_1[16] D=alu_in_2[0] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_1_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate LUT4 A=$false B=alu_in_2[2] C=alu_in_2[3] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate LUT4 A=alu_in_1[30] B=alu_in_2[30] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[30] D=alu_in_2[30] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[30] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_ALUT BLUT=alu_output_PFUMX_Z_2_BLUT C0=alu_output_PFUMX_Z_2_C0[4] Z=alu_output[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_2_C0[0] B=alu_output_PFUMX_Z_2_C0[1] C=alu_output_PFUMX_Z_2_C0[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_2_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] Z=alu_output_PFUMX_Z_2_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_2_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000001000100 +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] C=alu_in_2[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010110011111111 +.gate LUT4 A=$false B=alu_in_1[28] C=alu_in_1[29] D=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[19] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[18] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[21] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[20] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] D=alu_in_2[5] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110100000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[17] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[16] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z C0=alu_in_2[1] Z=alu_output_LUT4_Z_9_B_LUT4_Z_1_B_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[26] C=alu_in_1[27] D=alu_in_2[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[1] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_PFUMX_Z_2_C0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] C=alu_output_LUT4_Z_9_B_LUT4_Z_1_C[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_2_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1111000100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_op_i[2] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=sum[27] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111110011 +.gate LUT4 A=$false B=sum[27] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_in_1[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001111110000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_in_1[27] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011111111 +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[0] B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[1] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_2_C0_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000000101 +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_ALUT BLUT=alu_output_PFUMX_Z_3_BLUT C0=alu_output_PFUMX_Z_3_C0[4] Z=alu_output[26] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_3_C0[0] B=alu_output_PFUMX_Z_3_C0[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] D=alu_output_PFUMX_Z_3_C0[3] Z=alu_output_PFUMX_Z_3_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111100001011 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_3_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_3_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100001111 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100001111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001100000011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] C=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] Z=alu_output_PFUMX_Z_3_C0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0011001100000011 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[26] C=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] D=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_3_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_3_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[26] D=alu_in_2[26] Z=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[26] D=alu_in_2[26] Z=alu_output_PFUMX_Z_3_C0_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_3_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_3_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000110000000101 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_3_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_4_ALUT BLUT=alu_output_PFUMX_Z_4_BLUT C0=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] Z=alu_output[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_4_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] C=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] D=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_4_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0001111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_5_ALUT BLUT=alu_output_PFUMX_Z_5_BLUT C0=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[4] Z=alu_output[22] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_5_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] B=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[1] C=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] D=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_5_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0001111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_6_ALUT BLUT=alu_output_PFUMX_Z_6_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[4] Z=alu_output[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_6_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111010011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_6_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_7_ALUT BLUT=alu_output_PFUMX_Z_7_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] Z=alu_output[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[0] B=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_7_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111100011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[3] Z=alu_output_PFUMX_Z_7_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_8_ALUT BLUT=alu_output_PFUMX_Z_8_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[4] Z=alu_output[16] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[0] B=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] Z=alu_output_PFUMX_Z_8_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0100010011110100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_8_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_ALUT BLUT=alu_output_PFUMX_Z_9_BLUT C0=alu_output_PFUMX_Z_9_C0[4] Z=alu_output[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_9_C0[0] B=alu_output_PFUMX_Z_9_C0[1] C=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] D=alu_output_PFUMX_Z_9_C0[3] Z=alu_output_PFUMX_Z_9_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111111111100000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] B=alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[2] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_9_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_9_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_9_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1010001100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=alu_in_1[13] C=alu_in_1[14] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[11] C=alu_in_1[12] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] D=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0011001100001111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z C0=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[4] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=alu_in_2[31] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 1111111111110000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_2[6] D=alu_in_1[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_2[6] D=alu_in_1[6] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT C0=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 SD=alu_in_2[4] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[31] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000100000000 +.gate LUT4 A=alu_op_i[1] B=alu_op_i[2] C=alu_in_2[6] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=alu_op_i[2] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111100 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000011110000 +.gate LUT4 A=$false B=alu_in_1[9] C=alu_in_1[10] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_1[7] C=alu_in_1[8] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011001111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_op_i[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=sum[22] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111110011 +.gate LUT4 A=$false B=sum[22] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_in_1[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001111110000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_in_1[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011111111 +.gate LUT4 A=$false B=$false C=alu_in_2[2] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] C=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] D=alu_in_2[2] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[24] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[22] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[25] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[23] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_1_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0 D1=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[20] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[18] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[21] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[19] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_2_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[28] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[26] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[29] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_1[27] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 0000000011111111 +.gate LUT4 A=alu_in_1[30] B=alu_in_1[31] C=alu_in_2[1] D=alu_in_2[0] Z=alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate PFUMX ALUT=alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] Z=alu_output_PFUMX_Z_9_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] B=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] C=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] D=sum[14] Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000011101110111 +.gate LUT4 A=$false B=$false C=alu_in_1[14] D=alu_in_2[14] Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 1111000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[14] D=alu_in_2[14] Z=alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_output_PFUMX_Z_C0[0] B=alu_output_PFUMX_Z_C0[1] C=alu_output_PFUMX_Z_C0[2] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] Z=alu_output_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111110 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 1111111111111111 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] B=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] Z=alu_output_PFUMX_Z_C0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] B=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] C=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] D=alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] Z=alu_output_PFUMX_Z_C0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0101001100000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] D=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] C=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[23] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[22] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_1_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[25] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[24] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] C=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] Z=alu_output_PFUMX_Z_C0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000001100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000011111111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[30] C=alu_in_1[31] D=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0011001100001111 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[0] B=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] D=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 1111000001000100 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_2_B_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 1111111111111111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[3] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[2] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=$false C=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] D=alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000111100000000 +.gate LUT4 A=$false B=$false C=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:119.33-120.56" +.param INIT 0000111100000000 +.gate LUT4 A=alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] B=sum[7] C=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] D=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000000000111 +.gate LUT4 A=$false B=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] C=alu_in_2[3] D=alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011111100000000 +.gate LUT4 A=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] B=alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] C=alu_in_2[3] D=alu_in_2[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000110000001010 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_1[9] C=alu_in_1[10] D=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1111000011001100 +.gate LUT4 A=$false B=alu_in_1[7] C=alu_in_1[8] D=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000111100110011 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] C=alu_in_1[7] D=alu_in_2[7] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100000000000000 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[7] D=alu_in_2[7] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111100000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 SD=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:184.21-184.63" +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:182.21-182.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:178.19-178.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:160.39-161.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:158.39-159.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:179.19-179.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:165.39-166.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:163.39-164.56" +.param INIT 0000000000000000 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 SD=alu_in_2[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:183.21-183.64" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:180.19-180.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:170.39-171.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[15] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:168.39-169.56" +.param INIT 0000000000000011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_op_i[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:181.19-181.65" +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:175.41-176.56" +.param INIT 0000000000000000 +.gate LUT4 A=$false B=alu_in_1[14] C=alu_op_i[2] D=alu_in_2[6] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:173.41-174.56" +.param INIT 0000000000000011 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111100000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z BLUT=alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_1_Z_PFUMX_ALUT_Z +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_C[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=$false C=$false D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111111100000000 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_B[0] C=alu_output_LUT4_Z_A_LUT4_Z_1_C[4] D=alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011001111 +.gate LUT4 A=$false B=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[0] C=alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] C=alu_output_PFUMX_Z_C0_LUT4_Z_A[1] D=alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] D=alu_in_2[3] Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0011111110101111 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT C0=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] Z=alu_output_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:138.19-138.63" +.gate LUT4 A=alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] B=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:136.39-137.56" +.param INIT 0000000011110111 +.gate L6MUX21 D0=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 D1=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 SD=alu_op_i[2] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:154.21-154.62" +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT C0=alu_in_2[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:152.19-152.65" +.gate LUT4 A=$false B=sum[23] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:144.39-145.56" +.param INIT 1111111111110011 +.gate LUT4 A=$false B=sum[23] C=alu_op_i[1] D=alu_op_i[0] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:142.39-143.56" +.param INIT 1111111111110011 +.gate PFUMX ALUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT BLUT=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT C0=alu_in_2[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1 +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:153.19-153.65" +.gate LUT4 A=$false B=alu_op_i[1] C=alu_op_i[0] D=alu_in_1[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_ALUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:149.39-150.56" +.param INIT 0011001111110000 +.gate LUT4 A=$false B=$false C=alu_op_i[0] D=alu_in_1[23] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B_L6MUX21_Z_D1_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:147.39-148.56" +.param INIT 1111000011111111 +.gate LUT4 A=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] B=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] C=alu_in_2[3] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100010100000000 +.gate LUT4 A=$false B=alu_in_2[3] C=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] D=alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] Z=alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0011000000000000 +.gate LUT4 A=alu_in_2[0] B=alu_in_2[1] C=alu_in_2[2] D=alu_in_1[31] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate LUT4 A=$false B=$false C=$false D=$false Z=alu_output_PFUMX_Z_C0_PFUMX_Z_BLUT +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:134.39-135.56" +.param INIT 0000000000000000 +.gate LUT4 A=alu_in_1[31] B=alu_in_2[31] C=alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] D=alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000001111111 +.gate LUT4 A=alu_output_LUT4_Z_7_A_LUT4_Z_A[0] B=alu_output_LUT4_Z_7_A_LUT4_Z_A[1] C=alu_in_1[31] D=alu_in_2[31] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_C0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 1100111011100000 +.gate LUT4 A=alu_op_i[0] B=alu_op_i[1] C=alu_op_i[2] D=sum[31] Z=alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:128.32-129.56" +.param INIT 0000000100000000 +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[8] B1=complement2_CCU2C_S0_B0[9] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[8] COUT=complement2_CCU2C_S0_COUT[10] D0=$true D1=$true S0=complement2[8] S1=complement2[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[6] B1=complement2_CCU2C_S0_B0[7] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[6] COUT=complement2_CCU2C_S0_COUT[8] D0=$true D1=$true S0=complement2[6] S1=complement2[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[18] B1=complement2_CCU2C_S0_B0[19] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[18] COUT=complement2_CCU2C_S0_COUT[20] D0=$true D1=$true S0=complement2[18] S1=complement2[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[16] B1=complement2_CCU2C_S0_B0[17] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[16] COUT=complement2_CCU2C_S0_COUT[18] D0=$true D1=$true S0=complement2[16] S1=complement2[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[14] B1=complement2_CCU2C_S0_B0[15] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[14] COUT=complement2_CCU2C_S0_COUT[16] D0=$true D1=$true S0=complement2[14] S1=complement2[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[12] B1=complement2_CCU2C_S0_B0[13] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[12] COUT=complement2_CCU2C_S0_COUT[14] D0=$true D1=$true S0=complement2[12] S1=complement2[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[10] B1=complement2_CCU2C_S0_B0[11] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[10] COUT=complement2_CCU2C_S0_COUT[12] D0=$true D1=$true S0=complement2[10] S1=complement2[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$true A1=$false B0=complement2_CCU2C_S0_B0[0] B1=complement2_CCU2C_S0_B0[1] C0=$false C1=$false CIN=$false COUT=complement2_CCU2C_S0_COUT[2] D0=$true D1=$true S0=complement2[0] S1=complement2[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[4] B1=complement2_CCU2C_S0_B0[5] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[4] COUT=complement2_CCU2C_S0_COUT[6] D0=$true D1=$true S0=complement2[4] S1=complement2[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[30] B1=complement2_CCU2C_S0_B0[31] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[30] COUT=complement2_CCU2C_S0_3_COUT[31] D0=$true D1=$true S0=complement2[30] S1=complement2[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[2] B1=complement2_CCU2C_S0_B0[3] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[2] COUT=complement2_CCU2C_S0_COUT[4] D0=$true D1=$true S0=complement2[2] S1=complement2[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[28] B1=complement2_CCU2C_S0_B0[29] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[28] COUT=complement2_CCU2C_S0_COUT[30] D0=$true D1=$true S0=complement2[28] S1=complement2[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[26] B1=complement2_CCU2C_S0_B0[27] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[26] COUT=complement2_CCU2C_S0_COUT[28] D0=$true D1=$true S0=complement2[26] S1=complement2[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[24] B1=complement2_CCU2C_S0_B0[25] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[24] COUT=complement2_CCU2C_S0_COUT[26] D0=$true D1=$true S0=complement2[24] S1=complement2[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[22] B1=complement2_CCU2C_S0_B0[23] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[22] COUT=complement2_CCU2C_S0_COUT[24] D0=$true D1=$true S0=complement2[22] S1=complement2[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=$false A1=$false B0=complement2_CCU2C_S0_B0[20] B1=complement2_CCU2C_S0_B0[21] C0=$false C1=$false CIN=complement2_CCU2C_S0_COUT[20] COUT=complement2_CCU2C_S0_COUT[22] D0=$true D1=$true S0=complement2[20] S1=complement2[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:14.27-14.43|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[29] Z=complement2_CCU2C_S0_B0[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[31] Z=complement2_CCU2C_S0_B0[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[21] Z=complement2_CCU2C_S0_B0[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[20] Z=complement2_CCU2C_S0_B0[20] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[19] Z=complement2_CCU2C_S0_B0[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[18] Z=complement2_CCU2C_S0_B0[18] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[17] Z=complement2_CCU2C_S0_B0[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[16] Z=complement2_CCU2C_S0_B0[16] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[15] Z=complement2_CCU2C_S0_B0[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[14] Z=complement2_CCU2C_S0_B0[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[13] Z=complement2_CCU2C_S0_B0[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[12] Z=complement2_CCU2C_S0_B0[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[30] Z=complement2_CCU2C_S0_B0[30] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[11] Z=complement2_CCU2C_S0_B0[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[10] Z=complement2_CCU2C_S0_B0[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[9] Z=complement2_CCU2C_S0_B0[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[8] Z=complement2_CCU2C_S0_B0[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[7] Z=complement2_CCU2C_S0_B0[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[6] Z=complement2_CCU2C_S0_B0[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[5] Z=complement2_CCU2C_S0_B0[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[4] Z=complement2_CCU2C_S0_B0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[3] Z=complement2_CCU2C_S0_B0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[2] Z=complement2_CCU2C_S0_B0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[28] Z=complement2_CCU2C_S0_B0[28] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[1] Z=complement2_CCU2C_S0_B0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[0] Z=complement2_CCU2C_S0_B0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[27] Z=complement2_CCU2C_S0_B0[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[26] Z=complement2_CCU2C_S0_B0[26] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[25] Z=complement2_CCU2C_S0_B0[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[24] Z=complement2_CCU2C_S0_B0[24] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[23] Z=complement2_CCU2C_S0_B0[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=$false C=$false D=alu_in_2[22] Z=complement2_CCU2C_S0_B0[22] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:114.33-115.56" +.param INIT 0000000011111111 +.gate LUT4 A=$false B=alu_in_2[31] C=complement2[31] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[30] C=complement2[30] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[30] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[21] C=complement2[21] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[20] C=complement2[20] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[20] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[19] C=complement2[19] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[18] C=complement2[18] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[18] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[17] C=complement2[17] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[16] C=complement2[16] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[16] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[15] C=complement2[15] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[14] C=complement2[14] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[14] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[13] C=complement2[13] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[12] C=complement2[12] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[12] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[29] C=complement2[29] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[11] C=complement2[11] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[10] C=complement2[10] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[10] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[9] C=complement2[9] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[8] C=complement2[8] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[8] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[7] C=complement2[7] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[6] C=complement2[6] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[6] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[5] C=complement2[5] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[4] C=complement2[4] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[4] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[3] C=complement2[3] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[2] C=complement2[2] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[28] C=complement2[28] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[28] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[1] C=complement2[1] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[0] C=complement2[0] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[0] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[27] C=complement2[27] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[26] C=complement2[26] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[26] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[25] C=complement2[25] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[24] C=complement2[24] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[24] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[23] C=complement2[23] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_in_2[22] C=complement2[22] D=complement2_LUT4_C_D[2] Z=sum_CCU2C_S0_B0[22] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 1100110011110000 +.gate LUT4 A=$false B=alu_op_i[0] C=alu_op_i[1] D=alu_op_i[3] Z=complement2_LUT4_C_D[2] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "/usr/bin/../share/yosys/ecp5/cells_map.v:124.33-125.56" +.param INIT 0000000011001111 +.gate CCU2C A0=alu_in_1[8] A1=alu_in_1[9] B0=sum_CCU2C_S0_B0[8] B1=sum_CCU2C_S0_B0[9] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[8] COUT=sum_CCU2C_S0_COUT[10] D0=$true D1=$true S0=sum[8] S1=sum[9] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[6] A1=alu_in_1[7] B0=sum_CCU2C_S0_B0[6] B1=sum_CCU2C_S0_B0[7] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[6] COUT=sum_CCU2C_S0_COUT[8] D0=$true D1=$true S0=sum[6] S1=sum[7] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[18] A1=alu_in_1[19] B0=sum_CCU2C_S0_B0[18] B1=sum_CCU2C_S0_B0[19] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[18] COUT=sum_CCU2C_S0_COUT[20] D0=$true D1=$true S0=sum[18] S1=sum[19] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[16] A1=alu_in_1[17] B0=sum_CCU2C_S0_B0[16] B1=sum_CCU2C_S0_B0[17] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[16] COUT=sum_CCU2C_S0_COUT[18] D0=$true D1=$true S0=sum[16] S1=sum[17] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[14] A1=alu_in_1[15] B0=sum_CCU2C_S0_B0[14] B1=sum_CCU2C_S0_B0[15] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[14] COUT=sum_CCU2C_S0_COUT[16] D0=$true D1=$true S0=sum[14] S1=sum[15] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[12] A1=alu_in_1[13] B0=sum_CCU2C_S0_B0[12] B1=sum_CCU2C_S0_B0[13] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[12] COUT=sum_CCU2C_S0_COUT[14] D0=$true D1=$true S0=sum[12] S1=sum[13] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[10] A1=alu_in_1[11] B0=sum_CCU2C_S0_B0[10] B1=sum_CCU2C_S0_B0[11] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[10] COUT=sum_CCU2C_S0_COUT[12] D0=$true D1=$true S0=sum[10] S1=sum[11] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[0] A1=alu_in_1[1] B0=sum_CCU2C_S0_B0[0] B1=sum_CCU2C_S0_B0[1] C0=$false C1=$false CIN=$false COUT=sum_CCU2C_S0_COUT[2] D0=$true D1=$true S0=sum[0] S1=sum[1] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[4] A1=alu_in_1[5] B0=sum_CCU2C_S0_B0[4] B1=sum_CCU2C_S0_B0[5] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[4] COUT=sum_CCU2C_S0_COUT[6] D0=$true D1=$true S0=sum[4] S1=sum[5] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[30] A1=alu_in_1[31] B0=sum_CCU2C_S0_B0[30] B1=sum_CCU2C_S0_B0[31] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[30] COUT=sum_CCU2C_S0_3_COUT[31] D0=$true D1=$true S0=sum[30] S1=sum[31] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[2] A1=alu_in_1[3] B0=sum_CCU2C_S0_B0[2] B1=sum_CCU2C_S0_B0[3] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[2] COUT=sum_CCU2C_S0_COUT[4] D0=$true D1=$true S0=sum[2] S1=sum[3] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[28] A1=alu_in_1[29] B0=sum_CCU2C_S0_B0[28] B1=sum_CCU2C_S0_B0[29] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[28] COUT=sum_CCU2C_S0_COUT[30] D0=$true D1=$true S0=sum[28] S1=sum[29] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[26] A1=alu_in_1[27] B0=sum_CCU2C_S0_B0[26] B1=sum_CCU2C_S0_B0[27] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[26] COUT=sum_CCU2C_S0_COUT[28] D0=$true D1=$true S0=sum[26] S1=sum[27] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[24] A1=alu_in_1[25] B0=sum_CCU2C_S0_B0[24] B1=sum_CCU2C_S0_B0[25] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[24] COUT=sum_CCU2C_S0_COUT[26] D0=$true D1=$true S0=sum[24] S1=sum[25] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[22] A1=alu_in_1[23] B0=sum_CCU2C_S0_B0[22] B1=sum_CCU2C_S0_B0[23] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[22] COUT=sum_CCU2C_S0_COUT[24] D0=$true D1=$true S0=sum[22] S1=sum[23] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.gate CCU2C A0=alu_in_1[20] A1=alu_in_1[21] B0=sum_CCU2C_S0_B0[20] B1=sum_CCU2C_S0_B0[21] C0=$false C1=$false CIN=sum_CCU2C_S0_COUT[20] COUT=sum_CCU2C_S0_COUT[22] D0=$true D1=$true S0=sum[20] S1=sum[21] +.attr module_not_derived 00000000000000000000000000000001 +.attr src "alu6.v:15.19-15.108|/usr/bin/../share/yosys/ecp5/arith_map.v:74.7-80.4" +.param INIT0 1001011010101010 +.param INIT1 1001011010101010 +.param INJECT1_0 "NO" +.param INJECT1_1 "NO" +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B[2] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[2] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[2] +1 1 +.names alu_in_2[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[3] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[0] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[1] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[6] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[0] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_Z_1_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[6] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A[0] alu_output_LUT4_Z_3_C_LUT4_Z_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_3_C_LUT4_Z_C[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_A_LUT4_Z_D[0] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[0] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B[2] +1 1 +.names alu_in_1[7] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_in_1[8] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A_PFUMX_Z_ALUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[1] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[2] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[3] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[2] +1 1 +.names sum[21] alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z_PFUMX_Z_C0[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_A[5] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_LUT4_Z_A[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[0] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[2] +1 1 +.names sum[14] alu_output_PFUMX_Z_9_C0_PFUMX_Z_C0[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_A_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_10_B_LUT4_Z_1_B[3] +1 1 +.names alu_in_1[29] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[0] +1 1 +.names alu_in_2[29] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_D[2] +1 1 +.names sum[9] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_10_B_LUT4_Z_2_A[3] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_A_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] alu_output_LUT4_Z_A_LUT4_Z_1_B[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[4] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_10_C0_LUT4_Z_1_A[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[4] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z[5] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_10_C0[2] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_8_A_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_1_B_LUT4_Z_C[0] +1 1 +.names sum[28] alu_output_LUT4_Z_1_B_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[6] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[0] +1 1 +.names sum[24] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_9_C0[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_A_L6MUX21_Z_SD[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_A_L6MUX21_Z_SD[3] +1 1 +.names alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[0] alu_output_LUT4_Z_4_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_4_C[1] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_3_C0[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z[4] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_B_Z[1] +1 1 +.names alu_op_i[2] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_1_B[0] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_3_C[0] +1 1 +.names sum[20] alu_output_LUT4_Z_3_C[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_LUT4_Z_4_C_PFUMX_Z_C0[0] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_4_C_PFUMX_Z_C0[2] +1 1 +.names sum[19] alu_output_LUT4_Z_4_C_PFUMX_Z_C0[3] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[2] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[4] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[0] +1 1 +.names sum[16] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z_LUT4_Z_1_C[1] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[0] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[1] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_Z_A[6] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_1_B_LUT4_Z_1_A[4] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_1_B_LUT4_Z_1_A[5] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_C[0] +1 1 +.names sum[8] alu_output_LUT4_Z_10_B_LUT4_Z_C[1] +1 1 +.names alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[0] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[1] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z_LUT4_Z_1_A[3] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[3] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_B[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_B[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_B[5] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[5] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[6] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] alu_output_LUT4_Z_A_LUT4_Z_1_C[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_LUT4_Z_A_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] alu_output_LUT4_Z_A_LUT4_Z_1_C[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_C[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_C[6] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[0] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[4] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[6] +1 1 +.names sum[31] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[1] +1 1 +.names sum[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_op_i[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_op_i[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B[4] +1 1 +.names alu_op_i[2] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[0] +1 1 +.names sum[3] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D0_Z_L6MUX21_D1_Z[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[4] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_9_B_LUT4_Z_C[0] +1 1 +.names sum[11] alu_output_LUT4_Z_9_B_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_3_C0_LUT4_Z_C[0] +1 1 +.names sum[26] alu_output_PFUMX_Z_3_C0_LUT4_Z_C[1] +1 1 +.names alu_in_1[26] alu_output_LUT4_Z_7_A_LUT4_Z_A[2] +1 1 +.names alu_in_2[26] alu_output_LUT4_Z_7_A_LUT4_Z_A[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[3] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[4] +1 1 +.names alu_in_2[5] alu_output_LUT4_Z_5_B_LUT4_Z_A[3] +1 1 +.names alu_in_2[4] alu_output_LUT4_Z_5_B_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_5_B_LUT4_Z_A[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_12_C_LUT4_Z_C[0] +1 1 +.names sum[2] alu_output_LUT4_Z_12_C_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_LUT4_Z_12_C[0] +1 1 +.names alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_12_C[1] +1 1 +.names alu_output_LUT4_Z_5_B_LUT4_Z_A_PFUMX_Z_BLUT_LUT4_Z_B[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[0] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_5_B_LUT4_Z_A_LUT4_Z_B_LUT4_C_Z[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[13] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[0] +1 1 +.names alu_in_1[13] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[3] +1 1 +.names sum[13] alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[4] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A[5] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_8_A[1] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_PFUMX_Z_12_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[0] +1 1 +.names sum[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_C[1] +1 1 +.names alu_in_1[17] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[0] +1 1 +.names alu_in_2[17] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z_LUT4_Z_2_C_LUT4_Z_1_D[2] +1 1 +.names alu_in_1[5] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_in_1[6] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[0] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_2_A[0] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_LUT4_Z_1_A[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_11_C_LUT4_Z_C[0] +1 1 +.names sum[5] alu_output_LUT4_Z_11_C_LUT4_Z_C[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_8_A_LUT4_Z_1_C[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_8_A_LUT4_Z_1_C[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_2_B[0] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[0] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z[4] alu_output_LUT4_Z_5_B[1] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[1] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A[3] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A[4] +1 1 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alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z[6] +1 1 +.names alu_in_1[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[0] +1 1 +.names alu_in_1[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[1] +1 1 +.names alu_in_2[0] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[3] +1 1 +.names alu_in_2[3] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z[4] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_PFUMX_Z_ALUT_LUT4_Z_B_LUT4_B_Z[3] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[0] +1 1 +.names sum[4] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z_LUT4_Z_2_C[1] +1 1 +.names alu_in_2[18] alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[1] +1 1 +.names alu_output_LUT4_Z_7_A_LUT4_Z_A[1] alu_output_LUT4_Z_5_B_LUT4_Z_C_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_8_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_D_Z_PFUMX_ALUT_Z[2] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_10_C0_LUT4_Z_C[0] +1 1 +.names sum[10] alu_output_PFUMX_Z_10_C0_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[1] alu_output_LUT4_Z_3_C_LUT4_Z_A[1] +1 1 +.names alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_Z_A_LUT4_A_Z[4] alu_output_LUT4_Z_3_C_LUT4_Z_A[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[1] alu_output_LUT4_Z_3_C_LUT4_Z_A_LUT4_A_Z_PFUMX_ALUT_Z[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[3] +1 1 +.names alu_in_1[31] alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[0] +1 1 +.names alu_in_2[31] alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_PFUMX_Z_C0_PFUMX_Z_C0_LUT4_Z_D[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_C0_PFUMX_Z_C0[0] +1 1 +.names alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[1] alu_output_PFUMX_Z_C0_PFUMX_Z_C0[1] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_C0_PFUMX_Z_C0[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_2_C0[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_LUT4_Z_9_B_LUT4_Z_1_C[0] +1 1 +.names alu_output_LUT4_Z_9_B_LUT4_Z_1_B[0] alu_output_LUT4_Z_9_B_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_1_A_LUT4_D_Z_PFUMX_BLUT_Z_L6MUX21_D1_Z[5] alu_output_LUT4_Z_9_B_LUT4_Z_1_C[3] +1 1 +.names alu_in_2[16] complement2_LUT4_C_D[0] +1 1 +.names complement2[16] complement2_LUT4_C_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[4] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[3] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_Z_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_1_A[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_2_C0_LUT4_Z_B[1] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[0] +1 1 +.names sum[7] alu_output_PFUMX_Z_C0_LUT4_Z_A_LUT4_C_Z_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_C0_LUT4_Z_B_LUT4_B_Z[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_1_A[2] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[1] alu_output_PFUMX_Z_C0_LUT4_Z_A[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_C0_LUT4_Z_A[2] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[2] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_A_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[2] +1 1 +.names alu_in_2[1] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z_D[6] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[1] +1 1 +.names alu_output_PFUMX_Z_C0_LUT4_Z_1_A_LUT4_Z_C[3] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A[4] +1 1 +.names alu_in_1[30] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[0] +1 1 +.names alu_in_1[31] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[1] +1 1 +.names alu_in_2[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[3] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[4] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[4] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_2_C0_LUT4_Z_1_B_LUT4_Z_A_LUT4_A_B[6] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_C0_LUT4_Z_2_B[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_C0[3] +1 1 +.names alu_in_1[30] alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[0] +1 1 +.names alu_in_2[30] alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_A_LUT4_Z_C[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_C_LUT4_Z_D[2] +1 1 +.names alu_output_PFUMX_Z_1_C0_LUT4_Z_A[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_C[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_C[1] +1 1 +.names alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_A[3] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[0] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C_PFUMX_Z_ALUT_LUT4_Z_B[4] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[1] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[0] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[1] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD[4] alu_output_PFUMX_Z_1_C0_LUT4_Z_1_C[3] +1 1 +.names alu_output_LUT4_Z_6_A_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D[0] alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[2] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_C0_PFUMX_Z_ALUT_LUT4_Z_B[3] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_B_Z[3] alu_output_PFUMX_Z_1_C0[3] +1 1 +.names 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alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[4] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z[0] alu_output_PFUMX_Z_C0_LUT4_Z_B_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_11_C_PFUMX_Z_ALUT_LUT4_Z_A_LUT4_Z_B_LUT4_B_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z[0] alu_output_LUT4_Z_8_A_LUT4_Z_C[0] +1 1 +.names sum[12] alu_output_LUT4_Z_8_A_LUT4_Z_C[1] +1 1 +.names alu_output_LUT4_Z_A_LUT4_Z_1_C[4] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A_LUT4_B_Z[0] +1 1 +.names alu_in_2[31] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[0] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[1] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_Z_B[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[3] +1 1 +.names alu_in_2[1] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[4] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[5] +1 1 +.names alu_output_LUT4_Z_A_L6MUX21_Z_SD_LUT4_Z_D[5] alu_output_PFUMX_Z_9_C0_LUT4_Z_2_B_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_B_Z_PFUMX_BLUT_ALUT_LUT4_Z_D[6] +1 1 +.names alu_output_LUT4_Z_3_C_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_A_LUT4_D_Z[0] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[1] +1 1 +.names alu_in_2[2] alu_output_PFUMX_Z_1_C0_LUT4_Z_2_A[2] +1 1 +.names alu_output_LUT4_Z_10_B_LUT4_Z_1_B_LUT4_A_Z[2] alu_output_PFUMX_Z_9_C0_LUT4_Z_A[2] +1 1 +.names alu_in_2[3] alu_output_PFUMX_Z_9_C0_LUT4_Z_A[3] +1 1 +.names $true alu_output_LUT4_Z_A_LUT4_Z_1_B_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z_D_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_LUT4_A_Z_LUT4_D_Z_LUT4_Z_B_PFUMX_Z_ALUT_LUT4_Z_B_CCU2C_COUT_S0_CCU2C_S0_COUT[0] +1 1 +.names alu_in_2[2] alu_output_LUT4_Z_9_B_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z_D_LUT4_Z_B[2] +1 1 +.names $false complement2_CCU2C_S0_COUT[0] +1 1 +.names complement2_CCU2C_S0_B0[0] complement2_CCU2C_S0_COUT[1] +1 1 +.names complement2_CCU2C_S0_B0[0] complement2_CCU2C_S0_3_COUT[0] +1 1 +.names complement2_CCU2C_S0_COUT[2] complement2_CCU2C_S0_3_COUT[1] +1 1 +.names complement2_CCU2C_S0_COUT[3] complement2_CCU2C_S0_3_COUT[2] +1 1 +.names complement2_CCU2C_S0_COUT[4] complement2_CCU2C_S0_3_COUT[3] +1 1 +.names complement2_CCU2C_S0_COUT[5] complement2_CCU2C_S0_3_COUT[4] +1 1 +.names complement2_CCU2C_S0_COUT[6] complement2_CCU2C_S0_3_COUT[5] +1 1 +.names complement2_CCU2C_S0_COUT[7] complement2_CCU2C_S0_3_COUT[6] +1 1 +.names complement2_CCU2C_S0_COUT[8] complement2_CCU2C_S0_3_COUT[7] +1 1 +.names complement2_CCU2C_S0_COUT[9] complement2_CCU2C_S0_3_COUT[8] +1 1 +.names complement2_CCU2C_S0_COUT[10] complement2_CCU2C_S0_3_COUT[9] +1 1 +.names complement2_CCU2C_S0_COUT[11] complement2_CCU2C_S0_3_COUT[10] +1 1 +.names complement2_CCU2C_S0_COUT[12] complement2_CCU2C_S0_3_COUT[11] +1 1 +.names complement2_CCU2C_S0_COUT[13] complement2_CCU2C_S0_3_COUT[12] +1 1 +.names complement2_CCU2C_S0_COUT[14] complement2_CCU2C_S0_3_COUT[13] +1 1 +.names complement2_CCU2C_S0_COUT[15] complement2_CCU2C_S0_3_COUT[14] +1 1 +.names complement2_CCU2C_S0_COUT[16] complement2_CCU2C_S0_3_COUT[15] +1 1 +.names complement2_CCU2C_S0_COUT[17] complement2_CCU2C_S0_3_COUT[16] +1 1 +.names complement2_CCU2C_S0_COUT[18] complement2_CCU2C_S0_3_COUT[17] +1 1 +.names complement2_CCU2C_S0_COUT[19] complement2_CCU2C_S0_3_COUT[18] +1 1 +.names complement2_CCU2C_S0_COUT[20] complement2_CCU2C_S0_3_COUT[19] +1 1 +.names complement2_CCU2C_S0_COUT[21] complement2_CCU2C_S0_3_COUT[20] +1 1 +.names complement2_CCU2C_S0_COUT[22] complement2_CCU2C_S0_3_COUT[21] +1 1 +.names complement2_CCU2C_S0_COUT[23] complement2_CCU2C_S0_3_COUT[22] +1 1 +.names complement2_CCU2C_S0_COUT[24] complement2_CCU2C_S0_3_COUT[23] +1 1 +.names complement2_CCU2C_S0_COUT[25] complement2_CCU2C_S0_3_COUT[24] +1 1 +.names complement2_CCU2C_S0_COUT[26] complement2_CCU2C_S0_3_COUT[25] +1 1 +.names complement2_CCU2C_S0_COUT[27] complement2_CCU2C_S0_3_COUT[26] +1 1 +.names complement2_CCU2C_S0_COUT[28] complement2_CCU2C_S0_3_COUT[27] +1 1 +.names complement2_CCU2C_S0_COUT[29] complement2_CCU2C_S0_3_COUT[28] +1 1 +.names complement2_CCU2C_S0_COUT[30] complement2_CCU2C_S0_3_COUT[29] +1 1 +.names complement2_CCU2C_S0_COUT[31] complement2_CCU2C_S0_3_COUT[30] +1 1 +.names $false sum_CCU2C_S0_COUT[0] +1 1 +.names sum_CCU2C_S0_COUT[1] sum_CCU2C_S0_3_COUT[0] +1 1 +.names sum_CCU2C_S0_COUT[2] sum_CCU2C_S0_3_COUT[1] +1 1 +.names sum_CCU2C_S0_COUT[3] sum_CCU2C_S0_3_COUT[2] +1 1 +.names sum_CCU2C_S0_COUT[4] sum_CCU2C_S0_3_COUT[3] +1 1 +.names sum_CCU2C_S0_COUT[5] sum_CCU2C_S0_3_COUT[4] +1 1 +.names sum_CCU2C_S0_COUT[6] sum_CCU2C_S0_3_COUT[5] +1 1 +.names sum_CCU2C_S0_COUT[7] sum_CCU2C_S0_3_COUT[6] +1 1 +.names sum_CCU2C_S0_COUT[8] sum_CCU2C_S0_3_COUT[7] +1 1 +.names sum_CCU2C_S0_COUT[9] sum_CCU2C_S0_3_COUT[8] +1 1 +.names sum_CCU2C_S0_COUT[10] sum_CCU2C_S0_3_COUT[9] +1 1 +.names sum_CCU2C_S0_COUT[11] sum_CCU2C_S0_3_COUT[10] +1 1 +.names sum_CCU2C_S0_COUT[12] sum_CCU2C_S0_3_COUT[11] +1 1 +.names sum_CCU2C_S0_COUT[13] sum_CCU2C_S0_3_COUT[12] +1 1 +.names sum_CCU2C_S0_COUT[14] sum_CCU2C_S0_3_COUT[13] +1 1 +.names sum_CCU2C_S0_COUT[15] sum_CCU2C_S0_3_COUT[14] +1 1 +.names sum_CCU2C_S0_COUT[16] sum_CCU2C_S0_3_COUT[15] +1 1 +.names sum_CCU2C_S0_COUT[17] sum_CCU2C_S0_3_COUT[16] +1 1 +.names sum_CCU2C_S0_COUT[18] sum_CCU2C_S0_3_COUT[17] +1 1 +.names sum_CCU2C_S0_COUT[19] sum_CCU2C_S0_3_COUT[18] +1 1 +.names sum_CCU2C_S0_COUT[20] sum_CCU2C_S0_3_COUT[19] +1 1 +.names sum_CCU2C_S0_COUT[21] sum_CCU2C_S0_3_COUT[20] +1 1 +.names sum_CCU2C_S0_COUT[22] sum_CCU2C_S0_3_COUT[21] +1 1 +.names sum_CCU2C_S0_COUT[23] sum_CCU2C_S0_3_COUT[22] +1 1 +.names sum_CCU2C_S0_COUT[24] sum_CCU2C_S0_3_COUT[23] +1 1 +.names sum_CCU2C_S0_COUT[25] sum_CCU2C_S0_3_COUT[24] +1 1 +.names sum_CCU2C_S0_COUT[26] sum_CCU2C_S0_3_COUT[25] +1 1 +.names sum_CCU2C_S0_COUT[27] sum_CCU2C_S0_3_COUT[26] +1 1 +.names sum_CCU2C_S0_COUT[28] sum_CCU2C_S0_3_COUT[27] +1 1 +.names sum_CCU2C_S0_COUT[29] sum_CCU2C_S0_3_COUT[28] +1 1 +.names sum_CCU2C_S0_COUT[30] sum_CCU2C_S0_3_COUT[29] +1 1 +.names sum_CCU2C_S0_COUT[31] sum_CCU2C_S0_3_COUT[30] +1 1 +.end |