1 files changed, 14 insertions, 0 deletions
diff --git a/verilog/alu/v6/aluOp.vh b/verilog/alu/v6/aluOp.vh
new file mode 100644
index 0000000..0e8c41a
--- /dev/null
+++ b/verilog/alu/v6/aluOp.vh
@@ -0,0 +1,14 @@
+`ifndef ALU_OP
+`define ALU_OP
+// 1st bit that is no longer there == SUB/SRA/NONE
+`define ADDSUB          3'b000 
+`define XOR             3'b100
+`define OR              3'b110
+`define AND             3'b111
+`define SLL             3'b001
+`define SR              3'b101
+`define SLT             3'b010
+`define SLTU            3'b011
+`define NONE            3'b111
+
+`endif