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| author | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
|---|---|---|
| committer | joshua <joshua@fedora.framework> | 2022-05-14 23:30:38 -0500 |
| commit | b8936029065835366e9e057a219c0c5194db8662 (patch) | |
| tree | 31e50944ac6e23850f92bb0e0f6d851b74307f60 /verilog/alu/v6/aluOp.vh | |
| parent | d6b7d26cf51b4b3a7b5604f9b81bb43f55cbc33c (diff) | |
| download | riscv-processor-inorder-b8936029065835366e9e057a219c0c5194db8662.tar.gz | |
Verilog update
Diffstat (limited to 'verilog/alu/v6/aluOp.vh')
| -rw-r--r-- | verilog/alu/v6/aluOp.vh | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/verilog/alu/v6/aluOp.vh b/verilog/alu/v6/aluOp.vh new file mode 100644 index 0000000..0e8c41a --- /dev/null +++ b/verilog/alu/v6/aluOp.vh @@ -0,0 +1,14 @@ +`ifndef ALU_OP +`define ALU_OP +// 1st bit that is no longer there == SUB/SRA/NONE +`define ADDSUB 3'b000 +`define XOR 3'b100 +`define OR 3'b110 +`define AND 3'b111 +`define SLL 3'b001 +`define SR 3'b101 +`define SLT 3'b010 +`define SLTU 3'b011 +`define NONE 3'b111 + +`endif |